i2c.mfd

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

MDF Database:  version 1.0
MDF_INFO | i2c | XC95144XL-10-TQ144
MACROCELL | 6 | 7 | sda_buf
ATTRIBUTES | 8783778 | 0
OUTPUTMC | 9 | 6 | 7 | 0 | 16 | 0 | 15 | 4 | 16 | 0 | 17 | 6 | 6 | 6 | 8 | 6 | 9 | 6 | 10
INPUTS | 11 | main_state_FFd1  | main_state_FFd2  | sda  | inner_state_FFd3  | inner_state_FFd2  | $OpTx$$OpTx$FX_DC$39_INV$385  | EXP24_.EXP  | EXP25_.EXP  | clk  | rst  | link
INPUTMC | 9 | 0 | 16 | 0 | 15 | 6 | 7 | 5 | 15 | 5 | 6 | 2 | 1 | 6 | 6 | 6 | 8 | 6 | 3
INPUTP | 2 | 143 | 79
IMPORTS | 2 | 6 | 6 | 6 | 8
EQ | 58 | 
   sda.D = !main_state_FFd1 & !main_state_FFd2
	# sda & inner_state_FFd3 & inner_state_FFd2 & 
	$OpTx$$OpTx$FX_DC$39_INV$385
;Imported pterms FB7_7
	# sda & !phase3 & !phase0 & inner_state_FFd2
	# sda & !phase3 & !$OpTx$$OpTx$FX_DC$37_INV$384 & 
	!$OpTx$$OpTx$FX_DC$61_INV$389
	# sda & main_state_FFd2 & i2c_state_FFd2 & 
	!$OpTx$$OpTx$FX_DC$62_INV$390
	# sda & i2c_state_FFd3 & !i2c_state_FFd1 & 
	$OpTx$$OpTx$FX_DC$43_INV$386
	# sda & !phase0 & main_state_FFd1 & i2c_state_FFd1 & 
	!$OpTx$$OpTx$FX_DC$39_INV$385
;Imported pterms FB7_9
	# sda & !phase3 & main_state_FFd1 & i2c_state_FFd1 & 
	$OpTx$$OpTx$FX_DC$39_INV$385
	# sda & !inner_state_FFd4 & !inner_state_FFd3 & 
	$OpTx$$OpTx$FX_DC$52_INV$387 & !$OpTx$$OpTx$FX_DC$37_INV$384
	# sda & main_state_FFd1 & !inner_state_FFd2 & 
	i2c_state_FFd1 & $OpTx$FX_DC$63
	# phase3 & !i2c_state_FFd3 & !inner_state_FFd2 & 
	$OpTx$FX_DC$40 & $OpTx$FX_DC$58
	# inner_state_FFd1 & main_state_FFd1 & 
	inner_state_FFd3 & i2c_state_FFd1 & !$OpTx$$OpTx$FX_DC$53_INV$388
;Imported pterms FB7_10
	# sda & !phase3 & main_state_FFd2 & i2c_state_FFd2 & 
	!$OpTx$$OpTx$FX_DC$52_INV$387
	# phase3 & !inner_state_FFd1 & i2c_state_FFd3 & 
	inner_state_FFd2 & $OpTx$FX_DC$69
	# phase0 & sda.PIN & main_state_FFd1 & 
	i2c_state_FFd1 & !$OpTx$$OpTx$FX_DC$68_INV$391
	# phase0 & sda.PIN & !inner_state_FFd3 & 
	$OpTx$$OpTx$FX_DC$39_INV$385 & $OpTx$FX_DC$59
	# sda & !phase1 & !inner_state_FFd4 & 
	!inner_state_FFd3 & !inner_state_FFd2 & !$OpTx$$OpTx$FX_DC$37_INV$384
;Imported pterms FB7_11
	# sda & phase1 & !phase0 & inner_state_FFd1 & 
	main_state_FFd2 & i2c_state_FFd2
	# sda & !phase0 & !main_state_FFd2 & i2c_state_FFd2 & 
	!i2c_state_FFd1 & $OpTx$$OpTx$FX_DC$39_INV$385
	# sda & !inner_state_FFd4 & !inner_state_FFd3 & 
	i2c_state_FFd3 & !inner_state_FFd2 & !$OpTx$$OpTx$FX_DC$43_INV$386
	# phase3 & !inner_state_FFd4 & inner_state_FFd3 & 
	i2c_state_FFd3 & inner_state_FFd2 & $OpTx$FX_DC$47
	# phase1 & inner_state_FFd1 & main_state_FFd2 & 
	inner_state_FFd3 & i2c_state_FFd3 & i2c_state_FFd2
;Imported pterms FB7_12
	# phase3 & main_state_FFd1 & !inner_state_FFd3 & 
	i2c_state_FFd3 & !i2c_state_FFd2 & $OpTx$$OpTx$FX_DC$39_INV$385
	# phase3 & !inner_state_FFd4 & !inner_state_FFd1 & 
	!inner_state_FFd3 & !i2c_state_FFd3 & inner_state_FFd2 & 
	!i2c_state_FFd1 & $OpTx$$OpTx$FX_DC$43_INV$386
	# phase1 & phase0 & sda.PIN & inner_state_FFd4 & 
	inner_state_FFd1 & main_state_FFd2 & i2c_state_FFd3 & 
	i2c_state_FFd2;
   sda.CLK = clk;
   sda.AP = !rst;
   sda.OE = link;

MACROCELL | 3 | 8 | en_xhdl3<0>
ATTRIBUTES | 4588402 | 0
OUTPUTMC | 16 | 3 | 7 | 3 | 15 | 5 | 9 | 3 | 12 | 5 | 3 | 7 | 0 | 3 | 1 | 3 | 6 | 3 | 8 | 3 | 11 | 3 | 13 | 3 | 14 | 3 | 16 | 5 | 4 | 5 | 8 | 5 | 10
INPUTS | 20 | clk  | rst  | cnt_scan<0>  | cnt_scan<10>  | cnt_scan<1>  | cnt_scan<2>  | cnt_scan<3>  | cnt_scan<4>  | cnt_scan<5>  | cnt_scan<6>  | cnt_scan<7>  | cnt_scan<8>  | cnt_scan<9>  | cnt_scan<11>  | en<0>  | en<1>  | writeData_reg<0>  | writeData_reg<1>  | writeData_reg<2>  | writeData_reg<3>
INPUTMC | 18 | 2 | 3 | 3 | 13 | 2 | 13 | 2 | 12 | 1 | 5 | 1 | 4 | 3 | 5 | 3 | 4 | 3 | 3 | 3 | 16 | 3 | 17 | 3 | 9 | 3 | 8 | 3 | 10 | 2 | 17 | 2 | 16 | 2 | 15 | 2 | 14
INPUTP | 2 | 143 | 79
EXPORTS | 1 | 3 | 7
EQ | 11 | 
   en<0>.T = Vcc;
   en<0>.CLK = clk;
   en<0>.AR = !rst;
   en<0>.CE = cnt_scan<0> & cnt_scan<10> & cnt_scan<1> & 
	cnt_scan<2> & cnt_scan<3> & cnt_scan<4> & cnt_scan<5> & 
	cnt_scan<6> & cnt_scan<7> & cnt_scan<8> & cnt_scan<9> & 
	cnt_scan<11>;
    en_xhdl3<0>.EXP  =  !en<0> & en<1> & writeData_reg<0> & 
	!writeData_reg<1> & !writeData_reg<2> & !writeData_reg<3>
	# !en<0> & en<1> & !writeData_reg<0> & 
	!writeData_reg<1> & writeData_reg<2> & !writeData_reg<3>

MACROCELL | 3 | 10 | en_xhdl3<1>
ATTRIBUTES | 4588514 | 0
OUTPUTMC | 20 | 3 | 0 | 3 | 15 | 5 | 9 | 3 | 12 | 5 | 3 | 7 | 0 | 3 | 7 | 3 | 1 | 3 | 6 | 3 | 8 | 3 | 11 | 3 | 13 | 3 | 14 | 3 | 16 | 3 | 17 | 5 | 4 | 5 | 8 | 5 | 10 | 7 | 16 | 7 | 17
INPUTS | 14 | clk  | rst  | cnt_scan<0>  | cnt_scan<10>  | cnt_scan<1>  | cnt_scan<2>  | cnt_scan<3>  | cnt_scan<4>  | cnt_scan<5>  | cnt_scan<6>  | cnt_scan<7>  | cnt_scan<8>  | cnt_scan<9>  | cnt_scan<11>
INPUTMC | 12 | 2 | 3 | 3 | 13 | 2 | 13 | 2 | 12 | 1 | 5 | 1 | 4 | 3 | 5 | 3 | 4 | 3 | 3 | 3 | 16 | 3 | 17 | 3 | 9
INPUTP | 2 | 143 | 79
EXPORTS | 1 | 3 | 11
EQ | 8 | 
   en<1>.T = Vcc;
   en<1>.CLK = clk;
   en<1>.AP = !rst;
   en<1>.CE = cnt_scan<0> & cnt_scan<10> & cnt_scan<1> & 
	cnt_scan<2> & cnt_scan<3> & cnt_scan<4> & cnt_scan<5> & 
	cnt_scan<6> & cnt_scan<7> & cnt_scan<8> & cnt_scan<9> & 
	cnt_scan<11>;
    en_xhdl3<1>.EXP  =  Vcc

MACROCELL | 1 | 0 | phase3
ATTRIBUTES | 8520496 | 0
OUTPUTMC | 28 | 6 | 6 | 1 | 0 | 6 | 16 | 5 | 12 | 0 | 16 | 0 | 15 | 5 | 15 | 7 | 3 | 5 | 6 | 7 | 4 | 7 | 2 | 6 | 0 | 7 | 13 | 5 | 7 | 5 | 11 | 5 | 13 | 5 | 14 | 5 | 16 | 6 | 4 | 6 | 5 | 6 | 8 | 6 | 9 | 6 | 10 | 6 | 11 | 6 | 14 | 6 | 15 | 6 | 17 | 7 | 14
INPUTS | 11 | phase3  | clk_div<0>  | clk_div<1>  | clk_div<2>  | clk_div<3>  | clk_div<4>  | clk_div<5>  | clk_div<6>  | clk_div<7>  | clk  | rst
INPUTMC | 9 | 1 | 0 | 2 | 4 | 1 | 9 | 1 | 17 | 1 | 8 | 1 | 7 | 1 | 16 | 1 | 15 | 1 | 6
INPUTP | 2 | 143 | 79
EQ | 5 | 
   phase3.D = !phase3 & !clk_div<0> & clk_div<1> & !clk_div<2> & 
	clk_div<3> & !clk_div<4> & !clk_div<5> & clk_div<6> & 
	!clk_div<7>;
   phase3.CLK = clk;
   phase3.AR = !rst;

MACROCELL | 1 | 2 | phase1
ATTRIBUTES | 8520496 | 0
OUTPUTMC | 20 | 6 | 2 | 1 | 2 | 7 | 1 | 5 | 2 | 7 | 12 | 7 | 11 | 7 | 9 | 7 | 8 | 6 | 11 | 7 | 5 | 0 | 16 | 0 | 15 | 5 | 14 | 6 | 3 | 4 | 16 | 0 | 17 | 6 | 1 | 6 | 9 | 6 | 10 | 7 | 15
INPUTS | 11 | phase1  | clk_div<0>  | clk_div<1>  | clk_div<2>  | clk_div<3>  | clk_div<4>  | clk_div<5>  | clk_div<6>  | clk_div<7>  | clk  | rst
INPUTMC | 9 | 1 | 2 | 2 | 4 | 1 | 9 | 1 | 17 | 1 | 8 | 1 | 7 | 1 | 16 | 1 | 15 | 1 | 6
INPUTP | 2 | 143 | 79
EQ | 5 | 
   phase1.D = !phase1 & !clk_div<0> & !clk_div<1> & !clk_div<2> & 
	clk_div<3> & clk_div<4> & !clk_div<5> & !clk_div<6> & 
	!clk_div<7>;
   phase1.CLK = clk;
   phase1.AR = !rst;

MACROCELL | 0 | 8 | start_delaycnt
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 21 | 0 | 8 | 0 | 7 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 9 | 0 | 6 | 0 | 5 | 0 | 17 | 0 | 4 | 0 | 3 | 0 | 10 | 1 | 14 | 1 | 13 | 1 | 12 | 1 | 11 | 1 | 10 | 0 | 2 | 0 | 1 | 0 | 0
INPUTS | 27 | start_delaycnt  | cnt_delay<0>  | cnt_delay<10>  | cnt_delay<12>  | cnt_delay<13>  | cnt_delay<18>  | cnt_delay<8>  | cnt_delay<11>  | cnt_delay<14>  | cnt_delay<15>  | cnt_delay<16>  | cnt_delay<17>  | cnt_delay<19>  | cnt_delay<1>  | cnt_delay<2>  | cnt_delay<3>  | cnt_delay<4>  | cnt_delay<5>  | cnt_delay<6>  | cnt_delay<7>  | cnt_delay<9>  | main_state_FFd1  | main_state_FFd2  | wr_input  | rd_input  | clk  | rst
INPUTMC | 23 | 0 | 8 | 0 | 7 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 9 | 0 | 6 | 0 | 5 | 0 | 17 | 0 | 4 | 0 | 3 | 0 | 10 | 1 | 14 | 1 | 13 | 1 | 12 | 1 | 11 | 1 | 10 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 16 | 0 | 15
INPUTP | 4 | 112 | 109 | 143 | 79
EQ | 22 | 
   start_delaycnt.T = start_delaycnt & !cnt_delay<0> & cnt_delay<10> & 
	cnt_delay<12> & cnt_delay<13> & cnt_delay<18> & cnt_delay<8> & 
	!cnt_delay<11> & !cnt_delay<14> & !cnt_delay<15> & !cnt_delay<16> & 
	!cnt_delay<17> & cnt_delay<19> & !cnt_delay<1> & !cnt_delay<2> & 
	!cnt_delay<3> & !cnt_delay<4> & !cnt_delay<5> & !cnt_delay<6> & 
	!cnt_delay<7> & !cnt_delay<9> & !main_state_FFd1 & !main_state_FFd2
	# !rd_input & !start_delaycnt & !cnt_delay<0> & 
	!cnt_delay<10> & !cnt_delay<12> & !cnt_delay<13> & !cnt_delay<18> & 
	!cnt_delay<8> & !cnt_delay<11> & !cnt_delay<14> & !cnt_delay<15> & 
	!cnt_delay<16> & !cnt_delay<17> & !cnt_delay<19> & !cnt_delay<1> & 
	!cnt_delay<2> & !cnt_delay<3> & !cnt_delay<4> & !cnt_delay<5> & 
	!cnt_delay<6> & !cnt_delay<7> & !cnt_delay<9> & !main_state_FFd1 & 
	!main_state_FFd2
	# !wr_input & !start_delaycnt & !cnt_delay<0> & 
	!cnt_delay<10> & !cnt_delay<12> & !cnt_delay<13> & !cnt_delay<18> & 
	!cnt_delay<8> & !cnt_delay<11> & !cnt_delay<14> & !cnt_delay<15> & 
	!cnt_delay<16> & !cnt_delay<17> & !cnt_delay<19> & !cnt_delay<1> & 
	!cnt_delay<2> & !cnt_delay<3> & !cnt_delay<4> & !cnt_delay<5> & 
	!cnt_delay<6> & !cnt_delay<7> & !cnt_delay<9> & !main_state_FFd1 & 
	!main_state_FFd2;
   start_delaycnt.CLK = clk;
   start_delaycnt.AR = !rst;

MACROCELL | 1 | 3 | phase0
ATTRIBUTES | 8520496 | 0
OUTPUTMC | 7 | 6 | 6 | 1 | 3 | 6 | 12 | 2 | 5 | 6 | 9 | 6 | 10 | 6 | 11
INPUTS | 11 | phase0  | clk_div<0>  | clk_div<1>  | clk_div<2>  | clk_div<3>  | clk_div<4>  | clk_div<5>  | clk_div<6>  | clk_div<7>  | clk  | rst
INPUTMC | 9 | 1 | 3 | 2 | 4 | 1 | 9 | 1 | 17 | 1 | 8 | 1 | 7 | 1 | 16 | 1 | 15 | 1 | 6
INPUTP | 2 | 143 | 79
EQ | 5 | 
   phase0.D = !phase0 & clk_div<0> & clk_div<1> & !clk_div<2> & 
	!clk_div<3> & !clk_div<4> & clk_div<5> & clk_div<6> & 
	!clk_div<7>;
   phase0.CLK = clk;
   phase0.AR = !rst;

MACROCELL | 0 | 7 | cnt_delay<0>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 22 | 0 | 8 | 0 | 7 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 9 | 0 | 6 | 0 | 5 | 0 | 16 | 0 | 4 | 0 | 3 | 0 | 10 | 1 | 14 | 1 | 13 | 1 | 12 | 1 | 11 | 1 | 10 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 17
INPUTS | 23 | cnt_delay<0>  | cnt_delay<10>  | cnt_delay<12>  | cnt_delay<13>  | cnt_delay<18>  | cnt_delay<8>  | cnt_delay<11>  | cnt_delay<14>  | cnt_delay<15>  | cnt_delay<16>  | cnt_delay<17>  | cnt_delay<19>  | cnt_delay<1>  | cnt_delay<2>  | cnt_delay<3>  | cnt_delay<4>  | cnt_delay<5>  | cnt_delay<6>  | cnt_delay<7>  | cnt_delay<9>  | clk  | rst  | start_delaycnt
INPUTMC | 21 | 0 | 7 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 9 | 0 | 6 | 0 | 5 | 0 | 17 | 0 | 4 | 0 | 3 | 0 | 10 | 1 | 14 | 1 | 13 | 1 | 12 | 1 | 11 | 1 | 10 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 8
INPUTP | 2 | 143 | 79
EQ | 9 | 
   !cnt_delay<0>.T = !cnt_delay<0> & cnt_delay<10> & cnt_delay<12> & 
	cnt_delay<13> & cnt_delay<18> & cnt_delay<8> & !cnt_delay<11> & 
	!cnt_delay<14> & !cnt_delay<15> & !cnt_delay<16> & !cnt_delay<17> & 
	cnt_delay<19> & !cnt_delay<1> & !cnt_delay<2> & !cnt_delay<3> & 
	!cnt_delay<4> & !cnt_delay<5> & !cnt_delay<6> & !cnt_delay<7> & 
	!cnt_delay<9>;
   cnt_delay<0>.CLK = clk;
   cnt_delay<0>.AR = !rst;
   cnt_delay<0>.CE = start_delaycnt;

MACROCELL | 0 | 14 | cnt_delay<10>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 15 | 0 | 8 | 0 | 7 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 9 | 0 | 6 | 0 | 5 | 0 | 16 | 0 | 4 | 0 | 3 | 0 | 10 | 0 | 0 | 0 | 17
INPUTS | 23 | cnt_delay<0>  | cnt_delay<8>  | cnt_delay<1>  | cnt_delay<2>  | cnt_delay<3>  | cnt_delay<4>  | cnt_delay<5>  | cnt_delay<6>  | cnt_delay<7>  | cnt_delay<9>  | cnt_delay<10>  | cnt_delay<12>  | cnt_delay<13>  | cnt_delay<18>  | cnt_delay<11>  | cnt_delay<14>  | cnt_delay<15>  | cnt_delay<16>  | cnt_delay<17>  | cnt_delay<19>  | clk  | rst  | start_delaycnt
INPUTMC | 21 | 0 | 7 | 0 | 9 | 1 | 14 | 1 | 13 | 1 | 12 | 1 | 11 | 1 | 10 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 6 | 0 | 5 | 0 | 17 | 0 | 4 | 0 | 3 | 0 | 10 | 0 | 8
INPUTP | 2 | 143 | 79
EQ | 12 | 
   cnt_delay<10>.T = cnt_delay<0> & cnt_delay<8> & cnt_delay<1> & 
	cnt_delay<2> & cnt_delay<3> & cnt_delay<4> & cnt_delay<5> & 
	cnt_delay<6> & cnt_delay<7> & cnt_delay<9>
	# !cnt_delay<0> & cnt_delay<10> & cnt_delay<12> & 
	cnt_delay<13> & cnt_delay<18> & cnt_delay<8> & !cnt_delay<11> & 
	!cnt_delay<14> & !cnt_delay<15> & !cnt_delay<16> & !cnt_delay<17> & 
	cnt_delay<19> & !cnt_delay<1> & !cnt_delay<2> & !cnt_delay<3> & 
	!cnt_delay<4> & !cnt_delay<5> & !cnt_delay<6> & !cnt_delay<7> & 
	!cnt_delay<9>;
   cnt_delay<10>.CLK = clk;
   cnt_delay<10>.AR = !rst;
   cnt_delay<10>.CE = start_delaycnt;

MACROCELL | 0 | 13 | cnt_delay<12>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 14 | 0 | 8 | 0 | 7 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 9 | 0 | 5 | 0 | 16 | 0 | 4 | 0 | 3 | 0 | 10 | 0 | 0 | 0 | 17
INPUTS | 23 | cnt_delay<0>  | cnt_delay<10>  | cnt_delay<8>  | cnt_delay<11>  | cnt_delay<1>  | cnt_delay<2>  | cnt_delay<3>  | cnt_delay<4>  | cnt_delay<5>  | cnt_delay<6>  | cnt_delay<7>  | cnt_delay<9>  | cnt_delay<12>  | cnt_delay<13>  | cnt_delay<18>  | cnt_delay<14>  | cnt_delay<15>  | cnt_delay<16>  | cnt_delay<17>  | cnt_delay<19>  | clk  | rst  | start_delaycnt
INPUTMC | 21 | 0 | 7 | 0 | 14 | 0 | 9 | 0 | 6 | 1 | 14 | 1 | 13 | 1 | 12 | 1 | 11 | 1 | 10 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 5 | 0 | 17 | 0 | 4 | 0 | 3 | 0 | 10 | 0 | 8
INPUTP | 2 | 143 | 79
EQ | 13 | 
   cnt_delay<12>.T = cnt_delay<0> & cnt_delay<10> & cnt_delay<8> & 
	cnt_delay<11> & cnt_delay<1> & cnt_delay<2> & cnt_delay<3> & 
	cnt_delay<4> & cnt_delay<5> & cnt_delay<6> & cnt_delay<7> & 
	cnt_delay<9>
	# !cnt_delay<0> & cnt_delay<10> & cnt_delay<12> & 
	cnt_delay<13> & cnt_delay<18> & cnt_delay<8> & !cnt_delay<11> & 
	!cnt_delay<14> & !cnt_delay<15> & !cnt_delay<16> & !cnt_delay<17> & 
	cnt_delay<19> & !cnt_delay<1> & !cnt_delay<2> & !cnt_delay<3> & 
	!cnt_delay<4> & !cnt_delay<5> & !cnt_delay<6> & !cnt_delay<7> & 
	!cnt_delay<9>;
   cnt_delay<12>.CLK = clk;
   cnt_delay<12>.AR = !rst;
   cnt_delay<12>.CE = start_delaycnt;

MACROCELL | 0 | 12 | cnt_delay<13>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 14 | 0 | 8 | 0 | 7 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 9 | 0 | 5 | 0 | 16 | 0 | 4 | 0 | 3 | 0 | 10 | 0 | 0 | 0 | 17
INPUTS | 23 | cnt_delay<0>  | cnt_delay<10>  | cnt_delay<12>  | cnt_delay<8>  | cnt_delay<11>  | cnt_delay<1>  | cnt_delay<2>  | cnt_delay<3>  | cnt_delay<4>  | cnt_delay<5>  | cnt_delay<6>  | cnt_delay<7>  | cnt_delay<9>  | cnt_delay<13>  | cnt_delay<18>  | cnt_delay<14>  | cnt_delay<15>  | cnt_delay<16>  | cnt_delay<17>  | cnt_delay<19>  | clk  | rst  | start_delaycnt
INPUTMC | 21 | 0 | 7 | 0 | 14 | 0 | 13 | 0 | 9 | 0 | 6 | 1 | 14 | 1 | 13 | 1 | 12 | 1 | 11 | 1 | 10 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 12 | 0 | 11 | 0 | 5 | 0 | 17 | 0 | 4 | 0 | 3 | 0 | 10 | 0 | 8
INPUTP | 2 | 143 | 79
EQ | 13 | 
   cnt_delay<13>.T = cnt_delay<0> & cnt_delay<10> & cnt_delay<12> & 
	cnt_delay<8> & cnt_delay<11> & cnt_delay<1> & cnt_delay<2> & 
	cnt_delay<3> & cnt_delay<4> & cnt_delay<5> & cnt_delay<6> & 
	cnt_delay<7> & cnt_delay<9>
	# !cnt_delay<0> & cnt_delay<10> & cnt_delay<12> & 
	cnt_delay<13> & cnt_delay<18> & cnt_delay<8> & !cnt_delay<11> & 
	!cnt_delay<14> & !cnt_delay<15> & !cnt_delay<16> & !cnt_delay<17> &