i2c.tspec

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

AUTO_TS_F2F:FROM:phase2.Q:TO:phase2.D:1
AUTO_TS_P2F:FROM:clk:TO:phase2.D:1
AUTO_TS_F2F:FROM:phase1.Q:TO:readData_reg<0>.D:1
AUTO_TS_F2F:FROM:sda_buf.Q:TO:readData_reg<0>.D:1
AUTO_TS_F2F:FROM:link.Q:TO:readData_reg<0>.D:1
AUTO_TS_F2F:FROM:readData_reg<0>.Q:TO:readData_reg<0>.D:1
AUTO_TS_F2F:FROM:inner_state_FFd2.Q:TO:readData_reg<0>.D:1
AUTO_TS_F2F:FROM:inner_state_FFd4.Q:TO:readData_reg<0>.D:1
AUTO_TS_F2F:FROM:inner_state_FFd1.Q:TO:readData_reg<0>.D:1
AUTO_TS_F2F:FROM:inner_state_FFd3.Q:TO:readData_reg<0>.D:1
AUTO_TS_P2F:FROM:clk:TO:readData_reg<0>.D:1
AUTO_TS_P2F:FROM:sda:TO:readData_reg<0>.D:1
AUTO_TS_F2F:FROM:main_state_FFd1.Q:TO:readData_reg<0>.CE:1
AUTO_TS_F2F:FROM:i2c_state_FFd1.Q:TO:readData_reg<0>.CE:1
AUTO_TS_P2F:FROM:clk:TO:readData_reg<0>.CE:1
AUTO_TS_F2F:FROM:phase1.Q:TO:readData_reg<1>.D:1
AUTO_TS_F2F:FROM:readData_reg<0>.Q:TO:readData_reg<1>.D:1
AUTO_TS_F2F:FROM:readData_reg<1>.Q:TO:readData_reg<1>.D:1
AUTO_TS_F2F:FROM:inner_state_FFd2.Q:TO:readData_reg<1>.D:1
AUTO_TS_F2F:FROM:inner_state_FFd4.Q:TO:readData_reg<1>.D:1
AUTO_TS_F2F:FROM:inner_state_FFd1.Q:TO:readData_reg<1>.D:1
AUTO_TS_F2F:FROM:inner_state_FFd3.Q:TO:readData_reg<1>.D:1
AUTO_TS_P2F:FROM:clk:TO:readData_reg<1>.D:1
AUTO_TS_F2F:FROM:main_state_FFd1.Q:TO:readData_reg<1>.CE:1
AUTO_TS_F2F:FROM:i2c_state_FFd1.Q:TO:readData_reg<1>.CE:1
AUTO_TS_P2F:FROM:clk:TO:readData_reg<1>.CE:1
AUTO_TS_F2F:FROM:phase1.Q:TO:readData_reg<2>.D:1
AUTO_TS_F2F:FROM:readData_reg<1>.Q:TO:readData_reg<2>.D:1
AUTO_TS_F2F:FROM:readData_reg<2>.Q:TO:readData_reg<2>.D:1
AUTO_TS_F2F:FROM:inner_state_FFd2.Q:TO:readData_reg<2>.D:1
AUTO_TS_F2F:FROM:inner_state_FFd4.Q:TO:readData_reg<2>.D:1
AUTO_TS_F2F:FROM:inner_state_FFd1.Q:TO:readData_reg<2>.D:1
AUTO_TS_F2F:FROM:inner_state_FFd3.Q:TO:readData_reg<2>.D:1
AUTO_TS_P2F:FROM:clk:TO:readData_reg<2>.D:1
AUTO_TS_F2F:FROM:main_state_FFd1.Q:TO:readData_reg<2>.CE:1
AUTO_TS_F2F:FROM:i2c_state_FFd1.Q:TO:readData_reg<2>.CE:1
AUTO_TS_P2F:FROM:clk:TO:readData_reg<2>.CE:1
AUTO_TS_F2F:FROM:phase1.Q:TO:readData_reg<3>.D:1
AUTO_TS_F2F:FROM:inner_state_FFd3.Q:TO:readData_reg<3>.D:1
AUTO_TS_F2F:FROM:inner_state_FFd2.Q:TO:readData_reg<3>.D:1
AUTO_TS_F2F:FROM:inner_state_FFd4.Q:TO:readData_reg<3>.D:1
AUTO_TS_F2F:FROM:inner_state_FFd1.Q:TO:readData_reg<3>.D:1
AUTO_TS_F2F:FROM:readData_reg<2>.Q:TO:readData_reg<3>.D:1
AUTO_TS_F2F:FROM:readData_reg<3>.Q:TO:readData_reg<3>.D:1
AUTO_TS_P2F:FROM:clk:TO:readData_reg<3>.D:1
AUTO_TS_F2F:FROM:main_state_FFd1.Q:TO:readData_reg<3>.CE:1
AUTO_TS_F2F:FROM:i2c_state_FFd1.Q:TO:readData_reg<3>.CE:1
AUTO_TS_P2F:FROM:clk:TO:readData_reg<3>.CE:1
AUTO_TS_F2F:FROM:phase1.Q:TO:readData_reg<4>.D:1
AUTO_TS_F2F:FROM:readData_reg<3>.Q:TO:readData_reg<4>.D:1
AUTO_TS_F2F:FROM:readData_reg<4>.Q:TO:readData_reg<4>.D:1
AUTO_TS_F2F:FROM:inner_state_FFd2.Q:TO:readData_reg<4>.D:1
AUTO_TS_F2F:FROM:inner_state_FFd4.Q:TO:readData_reg<4>.D:1
AUTO_TS_F2F:FROM:inner_state_FFd1.Q:TO:readData_reg<4>.D:1
AUTO_TS_F2F:FROM:inner_state_FFd3.Q:TO:readData_reg<4>.D:1
AUTO_TS_P2F:FROM:clk:TO:readData_reg<4>.D:1
AUTO_TS_F2F:FROM:main_state_FFd1.Q:TO:readData_reg<4>.CE:1
AUTO_TS_F2F:FROM:i2c_state_FFd1.Q:TO:readData_reg<4>.CE:1
AUTO_TS_P2F:FROM:clk:TO:readData_reg<4>.CE:1
AUTO_TS_F2F:FROM:phase1.Q:TO:readData_reg<5>.D:1
AUTO_TS_F2F:FROM:readData_reg<4>.Q:TO:readData_reg<5>.D:1
AUTO_TS_F2F:FROM:readData_reg<5>.Q:TO:readData_reg<5>.D:1
AUTO_TS_F2F:FROM:inner_state_FFd2.Q:TO:readData_reg<5>.D:1
AUTO_TS_F2F:FROM:inner_state_FFd4.Q:TO:readData_reg<5>.D:1
AUTO_TS_F2F:FROM:inner_state_FFd1.Q:TO:readData_reg<5>.D:1
AUTO_TS_F2F:FROM:inner_state_FFd3.Q:TO:readData_reg<5>.D:1
AUTO_TS_P2F:FROM:clk:TO:readData_reg<5>.D:1
AUTO_TS_F2F:FROM:main_state_FFd1.Q:TO:readData_reg<5>.CE:1
AUTO_TS_F2F:FROM:i2c_state_FFd1.Q:TO:readData_reg<5>.CE:1
AUTO_TS_P2F:FROM:clk:TO:readData_reg<5>.CE:1
AUTO_TS_F2F:FROM:phase1.Q:TO:readData_reg<6>.D:1
AUTO_TS_F2F:FROM:readData_reg<5>.Q:TO:readData_reg<6>.D:1
AUTO_TS_F2F:FROM:readData_reg<6>.Q:TO:readData_reg<6>.D:1
AUTO_TS_F2F:FROM:inner_state_FFd2.Q:TO:readData_reg<6>.D:1
AUTO_TS_F2F:FROM:inner_state_FFd4.Q:TO:readData_reg<6>.D:1
AUTO_TS_F2F:FROM:inner_state_FFd1.Q:TO:readData_reg<6>.D:1
AUTO_TS_F2F:FROM:inner_state_FFd3.Q:TO:readData_reg<6>.D:1
AUTO_TS_P2F:FROM:clk:TO:readData_reg<6>.D:1
AUTO_TS_F2F:FROM:main_state_FFd1.Q:TO:readData_reg<6>.CE:1
AUTO_TS_F2F:FROM:i2c_state_FFd1.Q:TO:readData_reg<6>.CE:1
AUTO_TS_P2F:FROM:clk:TO:readData_reg<6>.CE:1
AUTO_TS_F2F:FROM:phase1.Q:TO:readData_reg<7>.D:1
AUTO_TS_F2F:FROM:readData_reg<6>.Q:TO:readData_reg<7>.D:1
AUTO_TS_F2F:FROM:readData_reg<7>.Q:TO:readData_reg<7>.D:1
AUTO_TS_F2F:FROM:inner_state_FFd2.Q:TO:readData_reg<7>.D:1
AUTO_TS_F2F:FROM:inner_state_FFd4.Q:TO:readData_reg<7>.D:1
AUTO_TS_F2F:FROM:inner_state_FFd1.Q:TO:readData_reg<7>.D:1
AUTO_TS_F2F:FROM:inner_state_FFd3.Q:TO:readData_reg<7>.D:1
AUTO_TS_P2F:FROM:clk:TO:readData_reg<7>.D:1
AUTO_TS_F2F:FROM:main_state_FFd1.Q:TO:readData_reg<7>.CE:1
AUTO_TS_F2F:FROM:i2c_state_FFd1.Q:TO:readData_reg<7>.CE:1
AUTO_TS_P2F:FROM:clk:TO:readData_reg<7>.CE:1
AUTO_TS_F2F:FROM:main_state_FFd1.Q:TO:writeData_reg<0>.CE:1
AUTO_TS_F2F:FROM:main_state_FFd2.Q:TO:writeData_reg<0>.CE:1
AUTO_TS_P2F:FROM:clk:TO:writeData_reg<0>.CE:1
AUTO_TS_F2F:FROM:main_state_FFd1.Q:TO:writeData_reg<1>.CE:1
AUTO_TS_F2F:FROM:main_state_FFd2.Q:TO:writeData_reg<1>.CE:1
AUTO_TS_P2F:FROM:clk:TO:writeData_reg<1>.CE:1
AUTO_TS_F2F:FROM:main_state_FFd1.Q:TO:writeData_reg<2>.CE:1
AUTO_TS_F2F:FROM:main_state_FFd2.Q:TO:writeData_reg<2>.CE:1
AUTO_TS_P2F:FROM:clk:TO:writeData_reg<2>.CE:1
AUTO_TS_F2F:FROM:main_state_FFd1.Q:TO:writeData_reg<3>.CE:1
AUTO_TS_F2F:FROM:main_state_FFd2.Q:TO:writeData_reg<3>.CE:1
AUTO_TS_P2F:FROM:clk:TO:writeData_reg<3>.CE:1
AUTO_TS_F2F:FROM:phase0.Q:TO:scl_xhdl1.D:1
AUTO_TS_F2F:FROM:main_state_FFd1.Q:TO:scl_xhdl1.D:1
AUTO_TS_F2F:FROM:main_state_FFd2.Q:TO:scl_xhdl1.D:1
AUTO_TS_F2F:FROM:phase2.Q:TO:scl_xhdl1.D:1
AUTO_TS_F2F:FROM:scl_xhdl1.Q:TO:scl_xhdl1.D:1
AUTO_TS_P2F:FROM:clk:TO:scl_xhdl1.D:1
AUTO_TS_F2F:FROM:main_state_FFd1.Q:TO:inner_state_FFd4.D:1
AUTO_TS_F2F:FROM:inner_state_FFd3.Q:TO:inner_state_FFd4.D:1
AUTO_TS_F2F:FROM:inner_state_FFd2.Q:TO:inner_state_FFd4.D:1
AUTO_TS_F2F:FROM:phase3.Q:TO:inner_state_FFd4.D:1
AUTO_TS_F2F:FROM:i2c_state_FFd2.Q:TO:inner_state_FFd4.D:1
AUTO_TS_F2F:FROM:main_state_FFd2.Q:TO:inner_state_FFd4.D:1
AUTO_TS_F2F:FROM:i2c_state_FFd3.Q:TO:inner_state_FFd4.D:1
AUTO_TS_F2F:FROM:inner_state_FFd1.Q:TO:inner_state_FFd4.D:1
AUTO_TS_F2F:FROM:inner_state_FFd4.Q:TO:inner_state_FFd4.D:1
AUTO_TS_F2F:FROM:i2c_state_FFd1.Q:TO:inner_state_FFd4.D:1
AUTO_TS_F2F:FROM:link.Q:TO:inner_state_FFd4.D:1
AUTO_TS_P2F:FROM:clk:TO:inner_state_FFd4.D:1
AUTO_TS_F2F:FROM:main_state_FFd1.Q:TO:inner_state_FFd1.D:1
AUTO_TS_F2F:FROM:inner_state_FFd3.Q:TO:inner_state_FFd1.D:1
AUTO_TS_F2F:FROM:inner_state_FFd2.Q:TO:inner_state_FFd1.D:1
AUTO_TS_F2F:FROM:phase3.Q:TO:inner_state_FFd1.D:1
AUTO_TS_F2F:FROM:inner_state_FFd4.Q:TO:inner_state_FFd1.D:1
AUTO_TS_F2F:FROM:inner_state_FFd1.Q:TO:inner_state_FFd1.D:1
AUTO_TS_F2F:FROM:i2c_state_FFd1.Q:TO:inner_state_FFd1.D:1
AUTO_TS_F2F:FROM:main_state_FFd2.Q:TO:inner_state_FFd1.D:1
AUTO_TS_F2F:FROM:i2c_state_FFd2.Q:TO:inner_state_FFd1.D:1
AUTO_TS_F2F:FROM:i2c_state_FFd3.Q:TO:inner_state_FFd1.D:1
AUTO_TS_P2F:FROM:clk:TO:inner_state_FFd1.D:1
AUTO_TS_F2F:FROM:main_state_FFd1.Q:TO:main_state_FFd1.D:1
AUTO_TS_F2F:FROM:sda_buf.Q:TO:main_state_FFd1.D:1
AUTO_TS_F2F:FROM:inner_state_FFd3.Q:TO:main_state_FFd1.D:1
AUTO_TS_F2F:FROM:phase1.Q:TO:main_state_FFd1.D:1
AUTO_TS_F2F:FROM:inner_state_FFd4.Q:TO:main_state_FFd1.D:1
AUTO_TS_F2F:FROM:inner_state_FFd1.Q:TO:main_state_FFd1.D:1
AUTO_TS_F2F:FROM:i2c_state_FFd2.Q:TO:main_state_FFd1.D:1
AUTO_TS_F2F:FROM:i2c_state_FFd1.Q:TO:main_state_FFd1.D:1
AUTO_TS_F2F:FROM:main_state_FFd2.Q:TO:main_state_FFd1.D:1
AUTO_TS_F2F:FROM:cnt_delay<0>.Q:TO:main_state_FFd1.D:1
AUTO_TS_F2F:FROM:cnt_delay<10>.Q:TO:main_state_FFd1.D:1
AUTO_TS_F2F:FROM:cnt_delay<12>.Q:TO:main_state_FFd1.D:1
AUTO_TS_F2F:FROM:cnt_delay<13>.Q:TO:main_state_FFd1.D:1
AUTO_TS_F2F:FROM:cnt_delay<18>.Q:TO:main_state_FFd1.D:1
AUTO_TS_F2F:FROM:cnt_delay<8>.Q:TO:main_state_FFd1.D:1
AUTO_TS_F2F:FROM:cnt_delay<11>.Q:TO:main_state_FFd1.D:1
AUTO_TS_F2F:FROM:cnt_delay<14>.Q:TO:main_state_FFd1.D:1
AUTO_TS_F2F:FROM:cnt_delay<15>.Q:TO:main_state_FFd1.D:1
AUTO_TS_F2F:FROM:cnt_delay<16>.Q:TO:main_state_FFd1.D:1
AUTO_TS_F2F:FROM:cnt_delay<17>.Q:TO:main_state_FFd1.D:1
AUTO_TS_F2F:FROM:cnt_delay<19>.Q:TO:main_state_FFd1.D:1
AUTO_TS_F2F:FROM:cnt_delay<1>.Q:TO:main_state_FFd1.D:1
AUTO_TS_F2F:FROM:cnt_delay<2>.Q:TO:main_state_FFd1.D:1
AUTO_TS_F2F:FROM:cnt_delay<3>.Q:TO:main_state_FFd1.D:1
AUTO_TS_F2F:FROM:cnt_delay<4>.Q:TO:main_state_FFd1.D:1
AUTO_TS_F2F:FROM:cnt_delay<5>.Q:TO:main_state_FFd1.D:1
AUTO_TS_F2F:FROM:cnt_delay<6>.Q:TO:main_state_FFd1.D:1
AUTO_TS_F2F:FROM:cnt_delay<7>.Q:TO:main_state_FFd1.D:1
AUTO_TS_F2F:FROM:cnt_delay<9>.Q:TO:main_state_FFd1.D:1
AUTO_TS_F2F:FROM:phase3.Q:TO:main_state_FFd1.D:1
AUTO_TS_F2F:FROM:i2c_state_FFd3.Q:TO:main_state_FFd1.D:1
AUTO_TS_P2F:FROM:clk:TO:main_state_FFd1.D:1
AUTO_TS_P2F:FROM:rd_input:TO:main_state_FFd1.D:1
AUTO_TS_P2F:FROM:wr_input:TO:main_state_FFd1.D:1
AUTO_TS_F2F:FROM:main_state_FFd1.Q:TO:main_state_FFd2.D:1
AUTO_TS_F2F:FROM:main_state_FFd2.Q:TO:main_state_FFd2.D:1
AUTO_TS_F2F:FROM:cnt_delay<0>.Q:TO:main_state_FFd2.D:1
AUTO_TS_F2F:FROM:cnt_delay<10>.Q:TO:main_state_FFd2.D:1
AUTO_TS_F2F:FROM:cnt_delay<12>.Q:TO:main_state_FFd2.D:1
AUTO_TS_F2F:FROM:cnt_delay<13>.Q:TO:main_state_FFd2.D:1
AUTO_TS_F2F:FROM:cnt_delay<18>.Q:TO:main_state_FFd2.D:1
AUTO_TS_F2F:FROM:cnt_delay<8>.Q:TO:main_state_FFd2.D:1
AUTO_TS_F2F:FROM:cnt_delay<11>.Q:TO:main_state_FFd2.D:1
AUTO_TS_F2F:FROM:cnt_delay<14>.Q:TO:main_state_FFd2.D:1
AUTO_TS_F2F:FROM:cnt_delay<15>.Q:TO:main_state_FFd2.D:1
AUTO_TS_F2F:FROM:cnt_delay<16>.Q:TO:main_state_FFd2.D:1
AUTO_TS_F2F:FROM:cnt_delay<17>.Q:TO:main_state_FFd2.D:1
AUTO_TS_F2F:FROM:cnt_delay<19>.Q:TO:main_state_FFd2.D:1
AUTO_TS_F2F:FROM:cnt_delay<1>.Q:TO:main_state_FFd2.D:1
AUTO_TS_F2F:FROM:cnt_delay<2>.Q:TO:main_state_FFd2.D:1
AUTO_TS_F2F:FROM:cnt_delay<3>.Q:TO:main_state_FFd2.D:1
AUTO_TS_F2F:FROM:cnt_delay<4>.Q:TO:main_state_FFd2.D:1
AUTO_TS_F2F:FROM:cnt_delay<5>.Q:TO:main_state_FFd2.D:1
AUTO_TS_F2F:FROM:cnt_delay<6>.Q:TO:main_state_FFd2.D:1
AUTO_TS_F2F:FROM:cnt_delay<7>.Q:TO:main_state_FFd2.D:1
AUTO_TS_F2F:FROM:cnt_delay<9>.Q:TO:main_state_FFd2.D:1
AUTO_TS_F2F:FROM:i2c_state_FFd2.Q:TO:main_state_FFd2.D:1
AUTO_TS_F2F:FROM:i2c_state_FFd3.Q:TO:main_state_FFd2.D:1
AUTO_TS_F2F:FROM:inner_state_FFd3.Q:TO:main_state_FFd2.D:1
AUTO_TS_F2F:FROM:phase3.Q:TO:main_state_FFd2.D:1
AUTO_TS_F2F:FROM:inner_state_FFd1.Q:TO:main_state_FFd2.D:1
AUTO_TS_F2F:FROM:sda_buf.Q:TO:main_state_FFd2.D:1
AUTO_TS_F2F:FROM:phase1.Q:TO:main_state_FFd2.D:1
AUTO_TS_F2F:FROM:inner_state_FFd4.Q:TO:main_state_FFd2.D:1
AUTO_TS_P2F:FROM:clk:TO:main_state_FFd2.D:1
AUTO_TS_P2F:FROM:wr_input:TO:main_state_FFd2.D:1
AUTO_TS_F2F:FROM:main_state_FFd1.Q:TO:inner_state_FFd3.D:1
AUTO_TS_F2F:FROM:inner_state_FFd3.Q:TO:inner_state_FFd3.D:1
AUTO_TS_F2F:FROM:inner_state_FFd2.Q:TO:inner_state_FFd3.D:1
AUTO_TS_F2F:FROM:phase3.Q:TO:inner_state_FFd3.D:1
AUTO_TS_F2F:FROM:inner_state_FFd4.Q:TO:inner_state_FFd3.D:1
AUTO_TS_F2F:FROM:i2c_state_FFd1.Q:TO:inner_state_FFd3.D:1
AUTO_TS_F2F:FROM:i2c_state_FFd3.Q:TO:inner_state_FFd3.D:1
AUTO_TS_F2F:FROM:main_state_FFd2.Q:TO:inner_state_FFd3.D:1
AUTO_TS_F2F:FROM:phase1.Q:TO:inner_state_FFd3.D:1
AUTO_TS_F2F:FROM:inner_state_FFd1.Q:TO:inner_state_FFd3.D:1
AUTO_TS_F2F:FROM:i2c_state_FFd2.Q:TO:inner_state_FFd3.D:1
AUTO_TS_P2F:FROM:clk:TO:inner_state_FFd3.D:1
AUTO_TS_F2F:FROM:main_state_FFd1.Q:TO:i2c_state_FFd3.D:1
AUTO_TS_F2F:FROM:main_state_FFd2.Q:TO:i2c_state_FFd3.D:1
AUTO_TS_F2F:FROM:inner_state_FFd3.Q:TO:i2c_state_FFd3.D:1
AUTO_TS_F2F:FROM:phase3.Q:TO:i2c_state_FFd3.D:1
AUTO_TS_F2F:FROM:inner_state_FFd4.Q:TO:i2c_state_FFd3.D:1
AUTO_TS_F2F:FROM:inner_state_FFd1.Q:TO:i2c_state_FFd3.D:1
AUTO_TS_F2F:FROM:i2c_state_FFd2.Q:TO:i2c_state_FFd3.D:1
AUTO_TS_F2F:FROM:i2c_state_FFd3.Q:TO:i2c_state_FFd3.D:1
AUTO_TS_P2F:FROM:clk:TO:i2c_state_FFd3.D:1
AUTO_TS_F2F:FROM:inner_state_FFd3.Q:TO:inner_state_FFd2.D:1
AUTO_TS_F2F:FROM:inner_state_FFd2.Q:TO:inner_state_FFd2.D:1
AUTO_TS_F2F:FROM:inner_state_FFd1.Q:TO:inner_state_FFd2.D:1
AUTO_TS_F2F:FROM:main_state_FFd1.Q:TO:inner_state_FFd2.D:1
AUTO_TS_F2F:FROM:i2c_state_FFd2.Q:TO:inner_state_FFd2.D:1
AUTO_TS_F2F:FROM:i2c_state_FFd3.Q:TO:inner_state_FFd2.D:1
AUTO_TS_F2F:FROM:phase3.Q:TO:inner_state_FFd2.D:1
AUTO_TS_F2F:FROM:inner_state_FFd4.Q:TO:inner_state_FFd2.D:1
AUTO_TS_F2F:FROM:main_state_FFd2.Q:TO:inner_state_FFd2.D:1
AUTO_TS_F2F:FROM:i2c_state_FFd1.Q:TO:inner_state_FFd2.D:1
AUTO_TS_P2F:FROM:clk:TO:inner_state_FFd2.D:1
AUTO_TS_F2F:FROM:main_state_FFd2.Q:TO:i2c_state_FFd2.D:1
AUTO_TS_F2F:FROM:i2c_state_FFd3.Q:TO:i2c_state_FFd2.D:1
AUTO_TS_F2F:FROM:inner_state_FFd3.Q:TO:i2c_state_FFd2.D:1
AUTO_TS_F2F:FROM:phase3.Q:TO:i2c_state_FFd2.D:1
AUTO_TS_F2F:FROM:inner_state_FFd4.Q:TO:i2c_state_FFd2.D:1
AUTO_TS_F2F:FROM:inner_state_FFd1.Q:TO:i2c_state_FFd2.D:1
AUTO_TS_F2F:FROM:i2c_state_FFd2.Q:TO:i2c_state_FFd2.D:1
AUTO_TS_F2F:FROM:main_state_FFd1.Q:TO:i2c_state_FFd2.D:1
AUTO_TS_F2F:FROM:i2c_state_FFd1.Q:TO:i2c_state_FFd2.D:1
AUTO_TS_P2F:FROM:clk:TO:i2c_state_FFd2.D:1
AUTO_TS_F2F:FROM:main_state_FFd1.Q:TO:i2c_state_FFd1.D:1
AUTO_TS_F2F:FROM:main_state_FFd2.Q:TO:i2c_state_FFd1.D:1
AUTO_TS_F2F:FROM:i2c_state_FFd1.Q:TO:i2c_state_FFd1.D:1
AUTO_TS_F2F:FROM:inner_state_FFd3.Q:TO:i2c_state_FFd1.D:1
AUTO_TS_F2F:FROM:phase3.Q:TO:i2c_state_FFd1.D:1
AUTO_TS_F2F:FROM:inner_state_FFd4.Q:TO:i2c_state_FFd1.D:1
AUTO_TS_F2F:FROM:inner_state_FFd1.Q:TO:i2c_state_FFd1.D:1
AUTO_TS_F2F:FROM:i2c_state_FFd2.Q:TO:i2c_state_FFd1.D:1
AUTO_TS_F2F:FROM:i2c_state_FFd3.Q:TO:i2c_state_FFd1.D:1
AUTO_TS_P2F:FROM:clk:TO:i2c_state_FFd1.D:1
AUTO_TS_F2F:FROM:inner_state_FFd3.Q:TO:link.D:1
AUTO_TS_F2F:FROM:inner_state_FFd2.Q:TO:link.D:1
AUTO_TS_F2F:FROM:link.Q:TO:link.D:1
AUTO_TS_F2F:FROM:inner_state_FFd4.Q:TO:link.D:1
AUTO_TS_F2F:FROM:inner_state_FFd1.Q:TO:link.D:1
AUTO_TS_F2F:FROM:phase1.Q:TO:link.D:1
AUTO_TS_F2F:FROM:i2c_state_FFd3.Q:TO:link.D:1
AUTO_TS_F2F:FROM:i2c_state_FFd2.Q:TO:link.D:1
AUTO_TS_F2F:FROM:i2c_state_FFd1.Q:TO:link.D:1
AUTO_TS_F2F:FROM:main_state_FFd2.Q:TO:link.D:1
AUTO_TS_F2F:FROM:main_state_FFd1.Q:TO:link.D:1
AUTO_TS_F2F:FROM:phase3.Q:TO:link.D:1
AUTO_TS_P2F:FROM:clk:TO:link.D:1
AUTO_TS_F2F:FROM:clk_div<0>.Q:TO:clk_div<1>.D:1
AUTO_TS_P2F:FROM:clk:TO:clk_div<1>.D:1
AUTO_TS_F2F:FROM:clk_div<0>.Q:TO:clk_div<2>.D:1