i2c.rpt

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

i2c_state_FFd2_T <= ((i2c_state_FFd3.EXP)
	OR (main_state_FFd1 AND NOT i2c_state_FFd2 AND 
	i2c_state_FFd1)
	OR (NOT main_state_FFd1 AND NOT main_state_FFd2 AND 
	i2c_state_FFd2)
	OR (phase3 AND inner_state_FFd4 AND inner_state_FFd1 AND 
	main_state_FFd1 AND NOT inner_state_FFd3 AND i2c_state_FFd3 AND 
	NOT i2c_state_FFd2));

FTCPE_i2c_state_FFd3: FTCPE port map (i2c_state_FFd3,i2c_state_FFd3_T,clk,NOT rst,'0');
i2c_state_FFd3_T <= ((i2c_state_FFd1.EXP)
	OR (NOT main_state_FFd1 AND NOT main_state_FFd2 AND 
	i2c_state_FFd3)
	OR (phase3 AND inner_state_FFd4 AND inner_state_FFd1 AND 
	main_state_FFd2 AND NOT inner_state_FFd3 AND NOT i2c_state_FFd3 AND 
	NOT i2c_state_FFd2));

FTCPE_inner_state_FFd1: FTCPE port map (inner_state_FFd1,inner_state_FFd1_T,clk,NOT rst,'0');
inner_state_FFd1_T <= ((en_2_OBUF$BUF4.EXP)
	OR (EXP17_.EXP)
	OR (phase3 AND NOT inner_state_FFd4 AND NOT inner_state_FFd1 AND 
	main_state_FFd1 AND NOT inner_state_FFd3 AND NOT i2c_state_FFd3 AND 
	inner_state_FFd2)
	OR (phase3 AND NOT inner_state_FFd4 AND NOT inner_state_FFd1 AND 
	main_state_FFd2 AND NOT inner_state_FFd3 AND i2c_state_FFd3 AND 
	inner_state_FFd2)
	OR (phase3 AND NOT inner_state_FFd4 AND NOT inner_state_FFd1 AND 
	main_state_FFd2 AND NOT inner_state_FFd3 AND inner_state_FFd2 AND 
	NOT i2c_state_FFd2));

FDCPE_inner_state_FFd2: FDCPE port map (inner_state_FFd2,inner_state_FFd2_D,clk,NOT rst,'0');
inner_state_FFd2_D <= ((EXP16_.EXP)
	OR (_11_.EXP)
	OR (NOT main_state_FFd1 AND NOT main_state_FFd2)
	OR (NOT phase3 AND NOT inner_state_FFd1 AND NOT inner_state_FFd2)
	OR (inner_state_FFd4 AND NOT inner_state_FFd1 AND 
	NOT inner_state_FFd2));

FTCPE_inner_state_FFd3: FTCPE port map (inner_state_FFd3,inner_state_FFd3_T,clk,NOT rst,'0');
inner_state_FFd3_T <= ((en_2_OBUF$BUF3.EXP)
	OR (en_2_OBUF$BUF2.EXP)
	OR (phase3 AND inner_state_FFd4 AND inner_state_FFd1 AND 
	main_state_FFd1 AND NOT inner_state_FFd3 AND i2c_state_FFd1)
	OR (phase3 AND inner_state_FFd4 AND main_state_FFd1 AND 
	NOT inner_state_FFd3 AND NOT inner_state_FFd2 AND NOT i2c_state_FFd2)
	OR (phase3 AND inner_state_FFd4 AND main_state_FFd2 AND 
	NOT inner_state_FFd3 AND NOT inner_state_FFd2 AND NOT i2c_state_FFd2));

FDCPE_inner_state_FFd4: FDCPE port map (inner_state_FFd4,inner_state_FFd4_D,clk,NOT rst,'0');
inner_state_FFd4_D <= ((EXP30_.EXP)
	OR (EXP31_.EXP)
	OR (NOT phase3 AND inner_state_FFd4 AND main_state_FFd1)
	OR (NOT phase3 AND inner_state_FFd4 AND main_state_FFd2)
	OR (inner_state_FFd1 AND main_state_FFd1 AND 
	inner_state_FFd3));

FDCPE_link: FDCPE port map (link,link_D,clk,NOT rst,'0');
link_D <= ((EXP21_.EXP)
	OR (EXP22_.EXP)
	OR (NOT main_state_FFd2 AND i2c_state_FFd3 AND 
	i2c_state_FFd2 AND NOT i2c_state_FFd1 AND NOT link)
	OR (phase1 AND inner_state_FFd1 AND NOT main_state_FFd1 AND 
	NOT inner_state_FFd3 AND inner_state_FFd2 AND i2c_state_FFd2 AND NOT link)
	OR (inner_state_FFd1 AND NOT inner_state_FFd3 AND 
	NOT i2c_state_FFd3 AND inner_state_FFd2 AND i2c_state_FFd2 AND 
	NOT i2c_state_FFd1 AND NOT link));


lowbit <= '0';

FTCPE_main_state_FFd1: FTCPE port map (main_state_FFd1,main_state_FFd1_T,clk,NOT rst,'0');
main_state_FFd1_T <= ((cnt_delay(15).EXP)
	OR (phase3 AND inner_state_FFd1 AND main_state_FFd1 AND 
	inner_state_FFd3 AND i2c_state_FFd2 AND i2c_state_FFd1)
	OR (sda AND phase1 AND inner_state_FFd4 AND 
	inner_state_FFd1 AND main_state_FFd1 AND NOT inner_state_FFd3 AND 
	NOT i2c_state_FFd3 AND NOT i2c_state_FFd1));

FTCPE_main_state_FFd2: FTCPE port map (main_state_FFd2,main_state_FFd2_T,clk,NOT rst,'0');
main_state_FFd2_T <= ((main_state_FFd1.EXP)
	OR (main_state_FFd2 AND NOT i2c_state_FFd3 AND 
	i2c_state_FFd2)
	OR (phase3 AND inner_state_FFd1 AND main_state_FFd2 AND 
	inner_state_FFd3 AND i2c_state_FFd2)
	OR (sda AND phase1 AND inner_state_FFd4 AND 
	inner_state_FFd1 AND main_state_FFd2 AND NOT inner_state_FFd3));

FDCPE_phase0: FDCPE port map (phase0,phase0_D,clk,NOT rst,'0');
phase0_D <= (NOT phase0 AND clk_div(0) AND clk_div(1) AND NOT clk_div(2) AND 
	NOT clk_div(3) AND NOT clk_div(4) AND clk_div(5) AND clk_div(6) AND 
	NOT clk_div(7));

FDCPE_phase1: FDCPE port map (phase1,phase1_D,clk,NOT rst,'0');
phase1_D <= (NOT phase1 AND NOT clk_div(0) AND NOT clk_div(1) AND NOT clk_div(2) AND 
	clk_div(3) AND clk_div(4) AND NOT clk_div(5) AND NOT clk_div(6) AND 
	NOT clk_div(7));

FDCPE_phase2: FDCPE port map (phase2,phase2_D,clk,NOT rst,'0');
phase2_D <= (NOT phase2 AND clk_div(0) AND NOT clk_div(1) AND NOT clk_div(2) AND 
	NOT clk_div(3) AND clk_div(4) AND clk_div(5) AND NOT clk_div(6) AND 
	NOT clk_div(7));

FDCPE_phase3: FDCPE port map (phase3,phase3_D,clk,NOT rst,'0');
phase3_D <= (NOT phase3 AND NOT clk_div(0) AND clk_div(1) AND NOT clk_div(2) AND 
	clk_div(3) AND NOT clk_div(4) AND NOT clk_div(5) AND clk_div(6) AND 
	NOT clk_div(7));

FTCPE_readData_reg0: FTCPE port map (readData_reg(0),seg_data_6_OBUF.EXP,clk,NOT rst,'0',readData_reg_CE(0));
readData_reg_CE(0) <= (main_state_FFd1 AND i2c_state_FFd1);

FTCPE_readData_reg1: FTCPE port map (readData_reg(1),readData_reg_T(1),clk,NOT rst,'0',readData_reg_CE(1));
readData_reg_T(1) <= ((NOT phase1)
	OR (_10_.EXP)
	OR (readData_reg(0) AND readData_reg(1)));
readData_reg_CE(1) <= (main_state_FFd1 AND i2c_state_FFd1);

FTCPE_readData_reg2: FTCPE port map (readData_reg(2),readData_reg_T(2),clk,NOT rst,'0',readData_reg_CE(2));
readData_reg_T(2) <= ((NOT phase1)
	OR ($OpTx$FX_DC$59.EXP));
readData_reg_CE(2) <= (main_state_FFd1 AND i2c_state_FFd1);

FTCPE_readData_reg3: FTCPE port map (readData_reg(3),readData_reg_T(3),clk,NOT rst,'0',readData_reg_CE(3));
readData_reg_T(3) <= ((NOT phase1)
	OR (readData_reg(4).EXP)
	OR (readData_reg(2).EXP)
	OR (readData_reg(2) AND readData_reg(3)));
readData_reg_CE(3) <= (main_state_FFd1 AND i2c_state_FFd1);

FTCPE_readData_reg4: FTCPE port map (readData_reg(4),EXP34_.EXP,clk,NOT rst,'0',readData_reg_CE(4));
readData_reg_CE(4) <= (main_state_FFd1 AND i2c_state_FFd1);

FTCPE_readData_reg5: FTCPE port map (readData_reg(5),readData_reg_T(5),clk,NOT rst,'0',readData_reg_CE(5));
readData_reg_T(5) <= ((NOT phase1)
	OR (lowbit_OBUF.EXP)
	OR (readData_reg(4) AND readData_reg(5)));
readData_reg_CE(5) <= (main_state_FFd1 AND i2c_state_FFd1);

FTCPE_readData_reg6: FTCPE port map (readData_reg(6),EXP32_.EXP,clk,NOT rst,'0',readData_reg_CE(6));
readData_reg_CE(6) <= (main_state_FFd1 AND i2c_state_FFd1);

FTCPE_readData_reg7: FTCPE port map (readData_reg(7),readData_reg_T(7),clk,NOT rst,'0',readData_reg_CE(7));
readData_reg_T(7) <= ((NOT phase1)
	OR (EXP33_.EXP)
	OR (readData_reg(6) AND readData_reg(7)));
readData_reg_CE(7) <= (main_state_FFd1 AND i2c_state_FFd1);

FDCPE_scl: FDCPE port map (scl,scl_D,clk,'0',NOT rst);
scl_D <= ((phase0)
	OR (NOT phase2 AND scl)
	OR (NOT main_state_FFd1 AND NOT main_state_FFd2));

FDCPE_sda: FDCPE port map (sda_I,sda,clk,'0',NOT rst);
sda <= ((EXP24_.EXP)
	OR (EXP25_.EXP)
	OR (NOT main_state_FFd1 AND NOT main_state_FFd2)
	OR (sda AND inner_state_FFd3 AND inner_state_FFd2 AND 
	$OpTx$$OpTx$FX_DC$39_INV$385));
sda <= sda_I when sda_OE = '1' else 'Z';
sda_OE <= link;


seg_data(0) <= '1';


seg_data(1) <= ((en_2_OBUF$BUF5.EXP)
	OR (cnt_scan(9).EXP)
	OR (NOT en(1) AND NOT readData_reg(1) AND NOT readData_reg(2) AND 
	NOT readData_reg(3))
	OR (en(1) AND writeData_reg(0) AND writeData_reg(1) AND 
	writeData_reg(2) AND NOT writeData_reg(3))
	OR (en(1) AND NOT writeData_reg(0) AND NOT writeData_reg(1) AND 
	writeData_reg(2) AND writeData_reg(3))
	OR (NOT en(1) AND readData_reg(0) AND readData_reg(1) AND 
	readData_reg(2) AND NOT readData_reg(3))
	OR (NOT en(1) AND NOT readData_reg(0) AND NOT readData_reg(1) AND 
	readData_reg(2) AND readData_reg(3)));


seg_data(2)_BUFR <= ((EXP14_.EXP)
	OR (cnt_scan(8).EXP)
	OR (en(0) AND NOT en(1) AND readData_reg(4))
	OR (en(0) AND NOT en(1) AND readData_reg(5))
	OR (en(0) AND NOT en(1) AND readData_reg(6))
	OR (en(0) AND NOT en(1) AND readData_reg(7))
	OR (en(0) AND NOT en(1) AND readData_reg(0) AND 
	readData_reg(1) AND NOT readData_reg(3)));


seg_data(2) <= seg_data(2)_BUFR;


seg_data(3) <= ((_12_.EXP)
	OR (en_2_OBUF.EXP)
	OR (en(0) AND NOT en(1) AND readData_reg(4))
	OR (en(0) AND NOT en(1) AND readData_reg(5))
	OR (en(0) AND NOT en(1) AND readData_reg(6))
	OR (en(0) AND NOT en(1) AND readData_reg(7))
	OR (en(0) AND NOT en(1) AND readData_reg(0) AND 
	NOT readData_reg(3)));


seg_data(4) <= seg_data(4)_BUFR;


seg_data(4)_BUFR <= ((en_2_OBUF$BUF0.EXP)
	OR (cnt_scan(10).EXP)
	OR (en(0) AND NOT en(1) AND readData_reg(4))
	OR (en(0) AND NOT en(1) AND readData_reg(5))
	OR (en(0) AND NOT en(1) AND readData_reg(6))
	OR (en(0) AND NOT en(1) AND readData_reg(7))
	OR (en(0) AND NOT en(1) AND readData_reg(0) AND 
	readData_reg(1) AND readData_reg(2)));


seg_data(5) <= ((EXP15_.EXP)
	OR (en(0) AND NOT en(1) AND readData_reg(4))
	OR (en(0) AND NOT en(1) AND readData_reg(5))
	OR (en(0) AND NOT en(1) AND readData_reg(6))
	OR (en(0) AND NOT en(1) AND readData_reg(7))
	OR (en(0) AND NOT en(1) AND NOT readData_reg(0) AND 
	readData_reg(2) AND readData_reg(3)));


seg_data(6) <= NOT (EXP35_.EXP);


seg_data(7) <= seg_data(7)_BUFR;


seg_data(7)_BUFR <= ((EXP13_.EXP)
	OR (en_xhdl3(0).EXP)
	OR (en(0) AND NOT en(1) AND readData_reg(4))
	OR (en(0) AND NOT en(1) AND readData_reg(5))
	OR (en(0) AND NOT en(1) AND readData_reg(6))
	OR (en(0) AND NOT en(1) AND readData_reg(7))
	OR (en(0) AND NOT en(1) AND readData_reg(0) AND 
	NOT readData_reg(1) AND readData_reg(2) AND readData_reg(3)));

FTCPE_start_delaycnt: FTCPE port map (start_delaycnt,start_delaycnt_T,clk,NOT rst,'0');
start_delaycnt_T <= ((start_delaycnt AND NOT cnt_delay(0) AND cnt_delay(10) AND 
	cnt_delay(12) AND cnt_delay(13) AND cnt_delay(18) AND cnt_delay(8) AND 
	NOT cnt_delay(11) AND NOT cnt_delay(14) AND NOT cnt_delay(15) AND NOT cnt_delay(16) AND 
	NOT cnt_delay(17) AND cnt_delay(19) AND NOT cnt_delay(1) AND NOT cnt_delay(2) AND 
	NOT cnt_delay(3) AND NOT cnt_delay(4) AND NOT cnt_delay(5) AND NOT cnt_delay(6) AND 
	NOT cnt_delay(7) AND NOT cnt_delay(9) AND NOT main_state_FFd1 AND NOT main_state_FFd2)
	OR (NOT rd_input AND NOT start_delaycnt AND NOT cnt_delay(0) AND 
	NOT cnt_delay(10) AND NOT cnt_delay(12) AND NOT cnt_delay(13) AND NOT cnt_delay(18) AND 
	NOT cnt_delay(8) AND NOT cnt_delay(11) AND NOT cnt_delay(14) AND NOT cnt_delay(15) AND 
	NOT cnt_delay(16) AND NOT cnt_delay(17) AND NOT cnt_delay(19) AND NOT cnt_delay(1) AND 
	NOT cnt_delay(2) AND NOT cnt_delay(3) AND NOT cnt_delay(4) AND NOT cnt_delay(5) AND 
	NOT cnt_delay(6) AND NOT cnt_delay(7) AND NOT cnt_delay(9) AND NOT main_state_FFd1 AND 
	NOT main_state_FFd2)
	OR (NOT wr_input AND NOT start_delaycnt AND NOT cnt_delay(0) AND 
	NOT cnt_delay(10) AND NOT cnt_delay(12) AND NOT cnt_delay