📄 i2c.rpt
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FTCPE_clk_div1: FTCPE port map (clk_div(1),clk_div(0),clk,NOT rst,'0');
FTCPE_clk_div2: FTCPE port map (clk_div(2),clk_div_T(2),clk,NOT rst,'0');
clk_div_T(2) <= ((NOT clk_div(0))
OR (NOT clk_div(1))
OR (NOT clk_div(2) AND NOT clk_div(3) AND NOT clk_div(4) AND
clk_div(5) AND clk_div(6) AND NOT clk_div(7)));
FTCPE_clk_div3: FTCPE port map (clk_div(3),clk_div_T(3),clk,NOT rst,'0');
clk_div_T(3) <= (clk_div(0) AND clk_div(1) AND clk_div(2));
FTCPE_clk_div4: FTCPE port map (clk_div(4),clk_div_T(4),clk,NOT rst,'0');
clk_div_T(4) <= (clk_div(0) AND clk_div(1) AND clk_div(2) AND
clk_div(3));
FTCPE_clk_div5: FTCPE port map (clk_div(5),clk_div_T(5),clk,NOT rst,'0');
clk_div_T(5) <= ((clk_div(0) AND clk_div(1) AND clk_div(2) AND
clk_div(3) AND clk_div(4))
OR (clk_div(0) AND clk_div(1) AND NOT clk_div(2) AND
NOT clk_div(3) AND NOT clk_div(4) AND clk_div(5) AND clk_div(6) AND
NOT clk_div(7)));
FTCPE_clk_div6: FTCPE port map (clk_div(6),clk_div_T(6),clk,NOT rst,'0');
clk_div_T(6) <= ((clk_div(0) AND clk_div(1) AND clk_div(2) AND
clk_div(3) AND clk_div(4) AND clk_div(5))
OR (clk_div(0) AND clk_div(1) AND NOT clk_div(2) AND
NOT clk_div(3) AND NOT clk_div(4) AND clk_div(5) AND clk_div(6) AND
NOT clk_div(7)));
FTCPE_clk_div7: FTCPE port map (clk_div(7),clk_div_T(7),clk,NOT rst,'0');
clk_div_T(7) <= (clk_div(0) AND clk_div(1) AND clk_div(2) AND
clk_div(3) AND clk_div(4) AND clk_div(5) AND clk_div(6));
FTCPE_cnt_delay0: FTCPE port map (cnt_delay(0),cnt_delay_T(0),clk,NOT rst,'0',start_delaycnt);
cnt_delay_T(0) <= (NOT cnt_delay(0) AND cnt_delay(10) AND cnt_delay(12) AND
cnt_delay(13) AND cnt_delay(18) AND cnt_delay(8) AND NOT cnt_delay(11) AND
NOT cnt_delay(14) AND NOT cnt_delay(15) AND NOT cnt_delay(16) AND NOT cnt_delay(17) AND
cnt_delay(19) AND NOT cnt_delay(1) AND NOT cnt_delay(2) AND NOT cnt_delay(3) AND
NOT cnt_delay(4) AND NOT cnt_delay(5) AND NOT cnt_delay(6) AND NOT cnt_delay(7) AND
NOT cnt_delay(9));
FTCPE_cnt_delay1: FTCPE port map (cnt_delay(1),cnt_delay(0),clk,NOT rst,'0',start_delaycnt);
FTCPE_cnt_delay2: FTCPE port map (cnt_delay(2),cnt_delay_T(2),clk,NOT rst,'0',start_delaycnt);
cnt_delay_T(2) <= (cnt_delay(0) AND cnt_delay(1));
FTCPE_cnt_delay3: FTCPE port map (cnt_delay(3),cnt_delay_T(3),clk,NOT rst,'0',start_delaycnt);
cnt_delay_T(3) <= (cnt_delay(0) AND cnt_delay(1) AND cnt_delay(2));
FTCPE_cnt_delay4: FTCPE port map (cnt_delay(4),cnt_delay_T(4),clk,NOT rst,'0',start_delaycnt);
cnt_delay_T(4) <= (cnt_delay(0) AND cnt_delay(1) AND cnt_delay(2) AND
cnt_delay(3));
FTCPE_cnt_delay5: FTCPE port map (cnt_delay(5),cnt_delay_T(5),clk,NOT rst,'0',start_delaycnt);
cnt_delay_T(5) <= (cnt_delay(0) AND cnt_delay(1) AND cnt_delay(2) AND
cnt_delay(3) AND cnt_delay(4));
FTCPE_cnt_delay6: FTCPE port map (cnt_delay(6),cnt_delay_T(6),clk,NOT rst,'0',start_delaycnt);
cnt_delay_T(6) <= (cnt_delay(0) AND cnt_delay(1) AND cnt_delay(2) AND
cnt_delay(3) AND cnt_delay(4) AND cnt_delay(5));
FTCPE_cnt_delay7: FTCPE port map (cnt_delay(7),cnt_delay_T(7),clk,NOT rst,'0',start_delaycnt);
cnt_delay_T(7) <= (cnt_delay(0) AND cnt_delay(1) AND cnt_delay(2) AND
cnt_delay(3) AND cnt_delay(4) AND cnt_delay(5) AND cnt_delay(6));
FTCPE_cnt_delay8: FTCPE port map (cnt_delay(8),cnt_delay_T(8),clk,NOT rst,'0',start_delaycnt);
cnt_delay_T(8) <= ((cnt_delay(0) AND cnt_delay(1) AND cnt_delay(2) AND
cnt_delay(3) AND cnt_delay(4) AND cnt_delay(5) AND cnt_delay(6) AND
cnt_delay(7))
OR (NOT cnt_delay(0) AND cnt_delay(10) AND cnt_delay(12) AND
cnt_delay(13) AND cnt_delay(18) AND cnt_delay(8) AND NOT cnt_delay(11) AND
NOT cnt_delay(14) AND NOT cnt_delay(15) AND NOT cnt_delay(16) AND NOT cnt_delay(17) AND
cnt_delay(19) AND NOT cnt_delay(1) AND NOT cnt_delay(2) AND NOT cnt_delay(3) AND
NOT cnt_delay(4) AND NOT cnt_delay(5) AND NOT cnt_delay(6) AND NOT cnt_delay(7) AND
NOT cnt_delay(9)));
FTCPE_cnt_delay9: FTCPE port map (cnt_delay(9),cnt_delay_T(9),clk,NOT rst,'0',start_delaycnt);
cnt_delay_T(9) <= (cnt_delay(0) AND cnt_delay(8) AND cnt_delay(1) AND
cnt_delay(2) AND cnt_delay(3) AND cnt_delay(4) AND cnt_delay(5) AND
cnt_delay(6) AND cnt_delay(7));
FTCPE_cnt_delay10: FTCPE port map (cnt_delay(10),cnt_delay_T(10),clk,NOT rst,'0',start_delaycnt);
cnt_delay_T(10) <= ((cnt_delay(0) AND cnt_delay(8) AND cnt_delay(1) AND
cnt_delay(2) AND cnt_delay(3) AND cnt_delay(4) AND cnt_delay(5) AND
cnt_delay(6) AND cnt_delay(7) AND cnt_delay(9))
OR (NOT cnt_delay(0) AND cnt_delay(10) AND cnt_delay(12) AND
cnt_delay(13) AND cnt_delay(18) AND cnt_delay(8) AND NOT cnt_delay(11) AND
NOT cnt_delay(14) AND NOT cnt_delay(15) AND NOT cnt_delay(16) AND NOT cnt_delay(17) AND
cnt_delay(19) AND NOT cnt_delay(1) AND NOT cnt_delay(2) AND NOT cnt_delay(3) AND
NOT cnt_delay(4) AND NOT cnt_delay(5) AND NOT cnt_delay(6) AND NOT cnt_delay(7) AND
NOT cnt_delay(9)));
FTCPE_cnt_delay11: FTCPE port map (cnt_delay(11),cnt_delay_T(11),clk,NOT rst,'0',start_delaycnt);
cnt_delay_T(11) <= (cnt_delay(0) AND cnt_delay(10) AND cnt_delay(8) AND
cnt_delay(1) AND cnt_delay(2) AND cnt_delay(3) AND cnt_delay(4) AND
cnt_delay(5) AND cnt_delay(6) AND cnt_delay(7) AND cnt_delay(9));
FTCPE_cnt_delay12: FTCPE port map (cnt_delay(12),cnt_delay_T(12),clk,NOT rst,'0',start_delaycnt);
cnt_delay_T(12) <= ((cnt_delay(0) AND cnt_delay(10) AND cnt_delay(8) AND
cnt_delay(11) AND cnt_delay(1) AND cnt_delay(2) AND cnt_delay(3) AND
cnt_delay(4) AND cnt_delay(5) AND cnt_delay(6) AND cnt_delay(7) AND
cnt_delay(9))
OR (NOT cnt_delay(0) AND cnt_delay(10) AND cnt_delay(12) AND
cnt_delay(13) AND cnt_delay(18) AND cnt_delay(8) AND NOT cnt_delay(11) AND
NOT cnt_delay(14) AND NOT cnt_delay(15) AND NOT cnt_delay(16) AND NOT cnt_delay(17) AND
cnt_delay(19) AND NOT cnt_delay(1) AND NOT cnt_delay(2) AND NOT cnt_delay(3) AND
NOT cnt_delay(4) AND NOT cnt_delay(5) AND NOT cnt_delay(6) AND NOT cnt_delay(7) AND
NOT cnt_delay(9)));
FTCPE_cnt_delay13: FTCPE port map (cnt_delay(13),cnt_delay_T(13),clk,NOT rst,'0',start_delaycnt);
cnt_delay_T(13) <= ((cnt_delay(0) AND cnt_delay(10) AND cnt_delay(12) AND
cnt_delay(8) AND cnt_delay(11) AND cnt_delay(1) AND cnt_delay(2) AND
cnt_delay(3) AND cnt_delay(4) AND cnt_delay(5) AND cnt_delay(6) AND
cnt_delay(7) AND cnt_delay(9))
OR (NOT cnt_delay(0) AND cnt_delay(10) AND cnt_delay(12) AND
cnt_delay(13) AND cnt_delay(18) AND cnt_delay(8) AND NOT cnt_delay(11) AND
NOT cnt_delay(14) AND NOT cnt_delay(15) AND NOT cnt_delay(16) AND NOT cnt_delay(17) AND
cnt_delay(19) AND NOT cnt_delay(1) AND NOT cnt_delay(2) AND NOT cnt_delay(3) AND
NOT cnt_delay(4) AND NOT cnt_delay(5) AND NOT cnt_delay(6) AND NOT cnt_delay(7) AND
NOT cnt_delay(9)));
FTCPE_cnt_delay14: FTCPE port map (cnt_delay(14),cnt_delay_T(14),clk,NOT rst,'0',start_delaycnt);
cnt_delay_T(14) <= (cnt_delay(0) AND cnt_delay(10) AND cnt_delay(12) AND
cnt_delay(13) AND cnt_delay(8) AND cnt_delay(11) AND cnt_delay(1) AND
cnt_delay(2) AND cnt_delay(3) AND cnt_delay(4) AND cnt_delay(5) AND
cnt_delay(6) AND cnt_delay(7) AND cnt_delay(9));
FTCPE_cnt_delay15: FTCPE port map (cnt_delay(15),cnt_delay(9).EXP,clk,NOT rst,'0',start_delaycnt);
FTCPE_cnt_delay16: FTCPE port map (cnt_delay(16),cnt_delay_T(16),clk,NOT rst,'0',start_delaycnt);
cnt_delay_T(16) <= (cnt_delay(0) AND cnt_delay(10) AND cnt_delay(12) AND
cnt_delay(13) AND cnt_delay(8) AND cnt_delay(11) AND cnt_delay(14) AND
cnt_delay(15) AND cnt_delay(1) AND cnt_delay(2) AND cnt_delay(3) AND
cnt_delay(4) AND cnt_delay(5) AND cnt_delay(6) AND cnt_delay(7) AND
cnt_delay(9));
FTCPE_cnt_delay17: FTCPE port map (cnt_delay(17),cnt_delay_T(17),clk,NOT rst,'0',start_delaycnt);
cnt_delay_T(17) <= (cnt_delay(0) AND cnt_delay(10) AND cnt_delay(12) AND
cnt_delay(13) AND cnt_delay(8) AND cnt_delay(11) AND cnt_delay(14) AND
cnt_delay(15) AND cnt_delay(16) AND cnt_delay(1) AND cnt_delay(2) AND
cnt_delay(3) AND cnt_delay(4) AND cnt_delay(5) AND cnt_delay(6) AND
cnt_delay(7) AND cnt_delay(9));
FTCPE_cnt_delay18: FTCPE port map (cnt_delay(18),cnt_delay_T(18),clk,NOT rst,'0',start_delaycnt);
cnt_delay_T(18) <= ((cnt_delay(0) AND cnt_delay(10) AND cnt_delay(12) AND
cnt_delay(13) AND cnt_delay(8) AND cnt_delay(11) AND cnt_delay(14) AND
cnt_delay(15) AND cnt_delay(16) AND cnt_delay(17) AND cnt_delay(1) AND
cnt_delay(2) AND cnt_delay(3) AND cnt_delay(4) AND cnt_delay(5) AND
cnt_delay(6) AND cnt_delay(7) AND cnt_delay(9))
OR (NOT cnt_delay(0) AND cnt_delay(10) AND cnt_delay(12) AND
cnt_delay(13) AND cnt_delay(18) AND cnt_delay(8) AND NOT cnt_delay(11) AND
NOT cnt_delay(14) AND NOT cnt_delay(15) AND NOT cnt_delay(16) AND NOT cnt_delay(17) AND
cnt_delay(19) AND NOT cnt_delay(1) AND NOT cnt_delay(2) AND NOT cnt_delay(3) AND
NOT cnt_delay(4) AND NOT cnt_delay(5) AND NOT cnt_delay(6) AND NOT cnt_delay(7) AND
NOT cnt_delay(9)));
FTCPE_cnt_delay19: FTCPE port map (cnt_delay(19),cnt_delay_T(19),clk,NOT rst,'0',start_delaycnt);
cnt_delay_T(19) <= ((cnt_delay(0) AND cnt_delay(10) AND cnt_delay(12) AND
cnt_delay(13) AND cnt_delay(18) AND cnt_delay(8) AND cnt_delay(11) AND
cnt_delay(14) AND cnt_delay(15) AND cnt_delay(16) AND cnt_delay(17) AND
cnt_delay(1) AND cnt_delay(2) AND cnt_delay(3) AND cnt_delay(4) AND
cnt_delay(5) AND cnt_delay(6) AND cnt_delay(7) AND cnt_delay(9))
OR (NOT cnt_delay(0) AND cnt_delay(10) AND cnt_delay(12) AND
cnt_delay(13) AND cnt_delay(18) AND cnt_delay(8) AND NOT cnt_delay(11) AND
NOT cnt_delay(14) AND NOT cnt_delay(15) AND NOT cnt_delay(16) AND NOT cnt_delay(17) AND
cnt_delay(19) AND NOT cnt_delay(1) AND NOT cnt_delay(2) AND NOT cnt_delay(3) AND
NOT cnt_delay(4) AND NOT cnt_delay(5) AND NOT cnt_delay(6) AND NOT cnt_delay(7) AND
NOT cnt_delay(9)));
FTCPE_cnt_scan0: FTCPE port map (cnt_scan(0),'1',clk,NOT rst,'0');
FTCPE_cnt_scan1: FTCPE port map (cnt_scan(1),cnt_scan(0),clk,NOT rst,'0');
FTCPE_cnt_scan2: FTCPE port map (cnt_scan(2),cnt_scan_T(2),clk,NOT rst,'0');
cnt_scan_T(2) <= (cnt_scan(0) AND cnt_scan(1));
FTCPE_cnt_scan3: FTCPE port map (cnt_scan(3),cnt_scan_T(3),clk,NOT rst,'0');
cnt_scan_T(3) <= (cnt_scan(0) AND cnt_scan(1) AND cnt_scan(2));
FTCPE_cnt_scan4: FTCPE port map (cnt_scan(4),cnt_scan_T(4),clk,NOT rst,'0');
cnt_scan_T(4) <= (cnt_scan(0) AND cnt_scan(1) AND cnt_scan(2) AND
cnt_scan(3));
FTCPE_cnt_scan5: FTCPE port map (cnt_scan(5),cnt_scan_T(5),clk,NOT rst,'0');
cnt_scan_T(5) <= (cnt_scan(0) AND cnt_scan(1) AND cnt_scan(2) AND
cnt_scan(3) AND cnt_scan(4));
FTCPE_cnt_scan6: FTCPE port map (cnt_scan(6),cnt_scan_T(6),clk,NOT rst,'0');
cnt_scan_T(6) <= (cnt_scan(0) AND cnt_scan(1) AND cnt_scan(2) AND
cnt_scan(3) AND cnt_scan(4) AND cnt_scan(5));
FTCPE_cnt_scan7: FTCPE port map (cnt_scan(7),cnt_scan_T(7),clk,NOT rst,'0');
cnt_scan_T(7) <= (cnt_scan(0) AND cnt_scan(1) AND cnt_scan(2) AND
cnt_scan(3) AND cnt_scan(4) AND cnt_scan(5) AND cnt_scan(6));
FTCPE_cnt_scan8: FTCPE port map (cnt_scan(8),cnt_scan_T(8),clk,NOT rst,'0');
cnt_scan_T(8) <= (cnt_scan(0) AND cnt_scan(1) AND cnt_scan(2) AND
cnt_scan(3) AND cnt_scan(4) AND cnt_scan(5) AND cnt_scan(6) AND
cnt_scan(7));
FTCPE_cnt_scan9: FTCPE port map (cnt_scan(9),cnt_scan_T(9),clk,NOT rst,'0');
cnt_scan_T(9) <= (cnt_scan(0) AND cnt_scan(1) AND cnt_scan(2) AND
cnt_scan(3) AND cnt_scan(4) AND cnt_scan(5) AND cnt_scan(6) AND
cnt_scan(7) AND cnt_scan(8));
FTCPE_cnt_scan10: FTCPE port map (cnt_scan(10),cnt_scan_T(10),clk,NOT rst,'0');
cnt_scan_T(10) <= (cnt_scan(0) AND cnt_scan(1) AND cnt_scan(2) AND
cnt_scan(3) AND cnt_scan(4) AND cnt_scan(5) AND cnt_scan(6) AND
cnt_scan(7) AND cnt_scan(8) AND cnt_scan(9));
FTCPE_cnt_scan11: FTCPE port map (cnt_scan(11),cnt_scan_T(11),clk,NOT rst,'0');
cnt_scan_T(11) <= (cnt_scan(0) AND cnt_scan(10) AND cnt_scan(1) AND
cnt_scan(2) AND cnt_scan(3) AND cnt_scan(4) AND cnt_scan(5) AND
cnt_scan(6) AND cnt_scan(7) AND cnt_scan(8) AND cnt_scan(9));
FTCPE_en0: FTCPE port map (en(0),'1',clk,NOT rst,'0',en_CE(0));
en_CE(0) <= (cnt_scan(0) AND cnt_scan(10) AND cnt_scan(1) AND
cnt_scan(2) AND cnt_scan(3) AND cnt_scan(4) AND cnt_scan(5) AND
cnt_scan(6) AND cnt_scan(7) AND cnt_scan(8) AND cnt_scan(9) AND
cnt_scan(11));
FTCPE_en1: FTCPE port map (en(1),'1',clk,'0',NOT rst,en_CE(1));
en_CE(1) <= (cnt_scan(0) AND cnt_scan(10) AND cnt_scan(1) AND
cnt_scan(2) AND cnt_scan(3) AND cnt_scan(4) AND cnt_scan(5) AND
cnt_scan(6) AND cnt_scan(7) AND cnt_scan(8) AND cnt_scan(9) AND
cnt_scan(11));
en(2) <= en_2_OBUF$BUF1.EXP;
en(3) <= '1';
en(4) <= '1';
en(5) <= EXP18_.EXP;
en(6) <= '1';
en(7) <= en_xhdl3(1).EXP;
FTCPE_i2c_state_FFd1: FTCPE port map (i2c_state_FFd1,i2c_state_FFd1_T,clk,NOT rst,'0');
i2c_state_FFd1_T <= ((NOT main_state_FFd1 AND NOT main_state_FFd2 AND
i2c_state_FFd1)
OR (phase3 AND inner_state_FFd4 AND inner_state_FFd1 AND
main_state_FFd1 AND NOT inner_state_FFd3 AND NOT i2c_state_FFd3 AND
i2c_state_FFd2 AND NOT i2c_state_FFd1));
FTCPE_i2c_state_FFd2: FTCPE port map (i2c_state_FFd2,i2c_state_FFd2_T,clk,NOT rst,'0');
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