i2c.rpt

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

seg_data<3>          10       5<-   0   0     FB6_10  115   I/O     O
seg_data<0>           0       0   /\2   3     FB6_11  119   I/O     O
en<3>                 0       0   \/1   4     FB6_12  120   I/O     O
inner_state_FFd1     11       6<-   0   0     FB6_13        (b)     (b)
(unused)              0       0   /\5   0     FB6_14  121   I/O     (b)
en<4>                 0       0   \/4   1     FB6_15  124   I/O     O
inner_state_FFd3     14       9<-   0   0     FB6_16  117   I/O     (b)
en<5>                 1       1<- /\5   0     FB6_17  125   I/O     O
(unused)              0       0     0   5     FB6_18        (b)     (b)

Signals Used by Logic in Function Block
  1: clk               11: main_state_FFd1   21: readData_reg<6> 
  2: en<0>             12: main_state_FFd2   22: readData_reg<7> 
  3: en<1>             13: phase1            23: rst 
  4: i2c_state_FFd1    14: phase3            24: seg_data<2>_BUFR 
  5: i2c_state_FFd2    15: readData_reg<0>   25: seg_data<4>_BUFR 
  6: i2c_state_FFd3    16: readData_reg<1>   26: seg_data<7>_BUFR 
  7: inner_state_FFd1  17: readData_reg<2>   27: writeData_reg<0> 
  8: inner_state_FFd2  18: readData_reg<3>   28: writeData_reg<1> 
  9: inner_state_FFd3  19: readData_reg<4>   29: writeData_reg<2> 
 10: inner_state_FFd4  20: readData_reg<5>   30: writeData_reg<3> 

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
$OpTx$FX_DC$69       ....X...XX.X..............XXX........... 7
seg_data<7>          .........................X.............. 1
readData_reg<1>      X..X..XXXXX.X.XX......X................. 11
seg_data<5>          .XX...........XXXXXXXX....XXXX.......... 14
inner_state_FFd2     X..XXXXXXXXX.X........X................. 12
seg_data<4>          ........................X............... 1
seg_data<2>          .......................X................ 1
seg_data<3>          .XX...........XXXXXXXX....XXXX.......... 14
seg_data<0>          ........................................ 0
en<3>                ........................................ 0
inner_state_FFd1     X..XXXXXXXXX.X........X................. 12
en<4>                ........................................ 0
inner_state_FFd3     X..XXXXXXXXXXX........X................. 13
en<5>                ........................................ 0
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB7  ***********************************
Number of function block inputs used/remaining:               33/21
Number of signals used by logic mapping into function block:  33
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0   /\5   0     FB7_1         (b)     (b)
(unused)              0       0   \/5   0     FB7_2   71    I/O     I
(unused)              0       0   \/5   0     FB7_3   75    I/O     (b)
link                 25      20<-   0   0     FB7_4         (b)     (b)
(unused)              0       0   /\5   0     FB7_5   74    I/O     (b)
(unused)              0       0   /\5   0     FB7_6   76    I/O     (b)
(unused)              0       0   \/5   0     FB7_7   77    I/O     (b)
sda                  28      23<-   0   0     FB7_8   78    I/O     I/O
(unused)              0       0   /\5   0     FB7_9   80    I/O     (b)
(unused)              0       0   /\5   0     FB7_10  79    I/O     (b)
(unused)              0       0   /\5   0     FB7_11  82    I/O     (b)
(unused)              0       0   /\3   2     FB7_12  85    I/O     (b)
scl                   5       0     0   0     FB7_13  81    I/O     O
(unused)              0       0     0   5     FB7_14  86    I/O     
(unused)              0       0   \/3   2     FB7_15  87    I/O     (b)
(unused)              0       0   \/5   0     FB7_16  83    I/O     (b)
inner_state_FFd4     23      18<-   0   0     FB7_17  88    I/O     (b)
(unused)              0       0   /\5   0     FB7_18        (b)     (b)

Signals Used by Logic in Function Block
  1: $OpTx$$OpTx$FX_DC$37_INV$384  12: $OpTx$FX_DC$59    23: inner_state_FFd4 
  2: $OpTx$$OpTx$FX_DC$39_INV$385  13: $OpTx$FX_DC$63    24: link 
  3: $OpTx$$OpTx$FX_DC$43_INV$386  14: $OpTx$FX_DC$69    25: main_state_FFd1 
  4: $OpTx$$OpTx$FX_DC$52_INV$387  15: sda.PIN           26: main_state_FFd2 
  5: $OpTx$$OpTx$FX_DC$53_INV$388  16: clk               27: phase0 
  6: $OpTx$$OpTx$FX_DC$61_INV$389  17: i2c_state_FFd1    28: phase1 
  7: $OpTx$$OpTx$FX_DC$62_INV$390  18: i2c_state_FFd2    29: phase2 
  8: $OpTx$$OpTx$FX_DC$68_INV$391  19: i2c_state_FFd3    30: phase3 
  9: $OpTx$FX_DC$40                20: inner_state_FFd1  31: rst 
 10: $OpTx$FX_DC$47                21: inner_state_FFd2  32: scl 
 11: $OpTx$FX_DC$58                22: inner_state_FFd3  33: sda 

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
link                 ...............XXXXXXXXXXX.X.XX......... 14
sda                  XXXXXXXXXXXXXXXXXXXXXXXXXXXX.XX.X....... 31
scl                  ...............X........XXX.X.XX........ 7
inner_state_FFd4     ...............XXXXXXXXXXX...XX......... 13
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB8  ***********************************
Number of function block inputs used/remaining:               28/26
Number of signals used by logic mapping into function block:  28
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
readData_reg<6>       8       5<- /\2   0     FB8_1         (b)     (b)
(unused)              0       0   /\5   0     FB8_2   91    I/O     (b)
i2c_state_FFd1        4       0   \/1   0     FB8_3   95    I/O     (b)
i2c_state_FFd3        5       1<- \/1   0     FB8_4   97    I/O     (b)
i2c_state_FFd2        6       1<-   0   0     FB8_5   92    I/O     (b)
readData_reg<7>       8       3<-   0   0     FB8_6   93    I/O     (b)
(unused)              0       0   /\3   2     FB8_7         (b)     (b)
lowbit                0       0   \/3   2     FB8_8   94    I/O     O
readData_reg<5>       8       3<-   0   0     FB8_9   96    I/O     (b)
(unused)              0       0   \/5   0     FB8_10  101   I/O     (b)
readData_reg<4>       8       5<- \/2   0     FB8_11  98    I/O     I
readData_reg<3>       8       3<-   0   0     FB8_12  100   I/O     I
readData_reg<2>       8       4<- /\1   0     FB8_13  103   I/O     (b)
$OpTx$FX_DC$59        3       2<- /\4   0     FB8_14  102   I/O     (b)
readData_reg<0>       8       5<- /\2   0     FB8_15  104   I/O     (b)
seg_data<6>          12      12<- /\5   0     FB8_16  107   I/O     O
(unused)              0       0   /\5   0     FB8_17  105   I/O     (b)
(unused)              0       0   /\5   0     FB8_18        (b)     (b)

Signals Used by Logic in Function Block
  1: sda.PIN           11: inner_state_FFd4  20: readData_reg<4> 
  2: clk               12: main_state_FFd1   21: readData_reg<5> 
  3: en<0>             13: main_state_FFd2   22: readData_reg<6> 
  4: en<1>             14: phase1            23: readData_reg<7> 
  5: i2c_state_FFd1    15: phase3            24: rst 
  6: i2c_state_FFd2    16: readData_reg<0>   25: writeData_reg<0> 
  7: i2c_state_FFd3    17: readData_reg<1>   26: writeData_reg<1> 
  8: inner_state_FFd1  18: readData_reg<2>   27: writeData_reg<2> 
  9: inner_state_FFd2  19: readData_reg<3>   28: writeData_reg<3> 
 10: inner_state_FFd3 

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
readData_reg<6>      .X..X..XXXXX.X......XX.X................ 11
i2c_state_FFd1       .X..XXXX.XXXX.X........X................ 11
i2c_state_FFd3       .X...XXX.XXXX.X........X................ 10
i2c_state_FFd2       .X..XXXX.XXXX.X........X................ 11
readData_reg<7>      .X..X..XXXXX.X.......XXX................ 11
lowbit               ........................................ 0
readData_reg<5>      .X..X..XXXXX.X.....XX..X................ 11
readData_reg<4>      .X..X..XXXXX.X....XX...X................ 11
readData_reg<3>      .X..X..XXXXX.X...XX....X................ 11
readData_reg<2>      .X..X..XXXXX.X..XX.....X................ 11
$OpTx$FX_DC$59       ....XXX....XX.X......................... 6
readData_reg<0>      XX..X..XXXXX.X.X.......X................ 11
seg_data<6>          ..XX...........XXXXXXXX.XXXX............ 14
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********


$OpTx$$OpTx$FX_DC$37_INV$384 <= (i2c_state_FFd2 AND i2c_state_FFd1);


$OpTx$$OpTx$FX_DC$39_INV$385 <= (inner_state_FFd4 AND inner_state_FFd1);


$OpTx$$OpTx$FX_DC$43_INV$386 <= (main_state_FFd1 AND i2c_state_FFd2);


$OpTx$$OpTx$FX_DC$52_INV$387 <= (inner_state_FFd1 AND inner_state_FFd2);


$OpTx$$OpTx$FX_DC$53_INV$388 <= (NOT sda AND NOT phase1);


$OpTx$$OpTx$FX_DC$61_INV$389 <= ((NOT inner_state_FFd4 AND NOT inner_state_FFd3 AND 
	NOT inner_state_FFd2)
	OR (inner_state_FFd1 AND NOT inner_state_FFd3 AND 
	inner_state_FFd2));


$OpTx$$OpTx$FX_DC$62_INV$390 <= ((NOT inner_state_FFd1 AND i2c_state_FFd3)
	OR (inner_state_FFd4 AND NOT inner_state_FFd3 AND 
	i2c_state_FFd3));


$OpTx$$OpTx$FX_DC$68_INV$391 <= ((inner_state_FFd4 AND inner_state_FFd1 AND 
	inner_state_FFd2)
	OR (NOT inner_state_FFd4 AND NOT inner_state_FFd1 AND 
	NOT inner_state_FFd3 AND NOT inner_state_FFd2));


$OpTx$FX_DC$40 <= ((NOT i2c_state_FFd2)
	OR (main_state_FFd1 AND NOT i2c_state_FFd1));


$OpTx$FX_DC$47 <= ((NOT i2c_state_FFd2)
	OR (writeData_reg(3) AND main_state_FFd2));


$OpTx$FX_DC$58 <= ((inner_state_FFd4 AND inner_state_FFd3)
	OR (NOT inner_state_FFd4 AND NOT inner_state_FFd3 AND link));


$OpTx$FX_DC$59 <= ((readData_reg(0).EXP)
	OR (NOT phase3 AND NOT i2c_state_FFd2));


$OpTx$FX_DC$63 <= ((NOT phase0)
	OR (NOT inner_state_FFd4 AND NOT inner_state_FFd1 AND 
	NOT inner_state_FFd3));


$OpTx$FX_DC$69 <= ((inner_state_FFd4 AND NOT inner_state_FFd3 AND 
	NOT i2c_state_FFd2)
	OR (writeData_reg(1) AND inner_state_FFd4 AND 
	main_state_FFd2 AND NOT inner_state_FFd3)
	OR (writeData_reg(0) AND NOT inner_state_FFd4 AND 
	main_state_FFd2 AND NOT inner_state_FFd3 AND i2c_state_FFd2)
	OR (writeData_reg(2) AND inner_state_FFd4 AND 
	main_state_FFd2 AND inner_state_FFd3 AND i2c_state_FFd2));

















































FTCPE_clk_div0: FTCPE port map (clk_div(0),'1',clk,NOT rst,'0');