i2c.rpt

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

 
cpldfit:  version H.42                              Xilinx Inc.
                                  Fitter Report
Design Name: i2c                                 Date:  2-21-2006, 10:46AM
Device Used: XC95144XL-10-TQ144
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
103/144 ( 72%) 507 /720  ( 70%) 203/432 ( 47%)   71 /144 ( 49%) 27 /117 ( 23%)

** Function Block Resources **

Function    Mcells      FB Inps     Pterms      IO          
Block       Used/Tot    Used/Tot    Used/Tot    Used/Tot    
FB1          18/18*      36/54       83/90       0/15
FB2          18/18*      24/54       63/90       0/15
FB3          18/18*      20/54       43/90       0/15
FB4          16/18       28/54       77/90       6/15
FB5           2/18        4/54        2/90       0/14
FB6          14/18       30/54       72/90       9/13
FB7           4/18       33/54       81/90       2/15
FB8          13/18       28/54       86/90       2/15
             -----       -----       -----      -----    
            103/144     203/432     507/720     19/117

* - Resource is exhausted

** Global Control Resources **

Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :    8           8    |  I/O              :    27     109
Output        :   18          18    |  GCK/IO           :     0       3
Bidirectional :    1           1    |  GTS/IO           :     0       4
GCK           :    0           0    |  GSR/IO           :     0       1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     27          27

** Power Data **

There are 103 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
**************************  Errors and Warnings  ***************************

WARNING:Cpld:896 - Unable to map all desired signals into function block, FB6,
   because too many function block product terms are required. Buffering output
   signal seg_data<7> to allow all signals assigned to this function block to be
   placed.
WARNING:Cpld:896 - Unable to map all desired signals into function block, FB6,
   because too many function block product terms are required. Buffering output
   signal seg_data<4> to allow all signals assigned to this function block to be
   placed.
WARNING:Cpld:896 - Unable to map all desired signals into function block, FB6,
   because too many function block product terms are required. Buffering output
   signal seg_data<2> to allow all signals assigned to this function block to be
   placed.
*************************  Summary of Mapped Logic  ************************

** 19 Outputs **

Signal                        Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                          Pts   Inps          No.  Type    Use     Mode Rate State
seg_data<1>                   12    14    FB4_1   118  I/O     O       STD  FAST 
en<2>                         1     0     FB4_2   126  I/O     O       STD  FAST 
en<6>                         0     0     FB4_3   133  I/O     O       STD  FAST 
en<0>                         3     14    FB4_9   131  I/O     O       STD  FAST RESET
en<1>                         3     14    FB4_11  132  I/O     O       STD  FAST RESET
en<7>                         1     0     FB4_12  134  I/O     O       STD  FAST 
seg_data<7>                   1     1     FB6_2   106  I/O     O       STD  FAST 
seg_data<5>                   10    14    FB6_4   111  I/O     O       STD  FAST 
seg_data<4>                   1     1     FB6_8   113  I/O     O       STD  FAST 
seg_data<2>                   1     1     FB6_9   116  I/O     O       STD  FAST 
seg_data<3>                   10    14    FB6_10  115  I/O     O       STD  FAST 
seg_data<0>                   0     0     FB6_11  119  I/O     O       STD  FAST 
en<3>                         0     0     FB6_12  120  I/O     O       STD  FAST 
en<4>                         0     0     FB6_15  124  I/O     O       STD  FAST 
en<5>                         1     0     FB6_17  125  I/O     O       STD  FAST 
sda                           28    31    FB7_8   78   I/O     I/O     STD  FAST RESET
scl                           5     7     FB7_13  81   I/O     O       STD  FAST RESET
lowbit                        0     0     FB8_8   94   I/O     O       STD  FAST 
seg_data<6>                   12    14    FB8_16  107  I/O     O       STD  FAST 

** 84 Buried Nodes **

Signal                        Total Total Loc     Pwr  Reg Init
Name                          Pts   Inps          Mode State
cnt_delay<9>                  4     12    FB1_1   STD  RESET
cnt_delay<7>                  4     10    FB1_2   STD  RESET
cnt_delay<6>                  4     9     FB1_3   STD  RESET
cnt_delay<17>                 4     20    FB1_4   STD  RESET
cnt_delay<16>                 4     19    FB1_5   STD  RESET
cnt_delay<14>                 4     17    FB1_6   STD  RESET
cnt_delay<11>                 4     14    FB1_7   STD  RESET
cnt_delay<0>                  4     23    FB1_8   STD  RESET
start_delaycnt                5     27    FB1_9   STD  RESET
cnt_delay<8>                  5     23    FB1_10  STD  RESET
cnt_delay<19>                 5     23    FB1_11  STD  RESET
cnt_delay<18>                 5     23    FB1_12  STD  RESET
cnt_delay<13>                 5     23    FB1_13  STD  RESET
cnt_delay<12>                 5     23    FB1_14  STD  RESET
cnt_delay<10>                 5     23    FB1_15  STD  RESET
main_state_FFd2               6     33    FB1_16  STD  RESET
main_state_FFd1               6     35    FB1_17  STD  RESET
cnt_delay<15>                 4     18    FB1_18  STD  RESET
phase3                        3     11    FB2_1   STD  RESET
phase2                        3     11    FB2_2   STD  RESET
phase1                        3     11    FB2_3   STD  RESET
phase0                        3     11    FB2_4   STD  RESET
cnt_scan<4>                   3     6     FB2_5   STD  RESET
cnt_scan<3>                   3     5     FB2_6   STD  RESET
clk_div<7>                    3     9     FB2_7   STD  RESET
clk_div<4>                    3     6     FB2_8   STD  RESET
clk_div<3>                    3     5     FB2_9   STD  RESET
clk_div<1>                    3     3     FB2_10  STD  RESET
cnt_delay<5>                  4     8     FB2_11  STD  RESET
cnt_delay<4>                  4     7     FB2_12  STD  RESET
cnt_delay<3>                  4     6     FB2_13  STD  RESET
cnt_delay<2>                  4     5     FB2_14  STD  RESET
cnt_delay<1>                  4     4     FB2_15  STD  RESET
clk_div<6>                    4     10    FB2_16  STD  RESET
clk_div<5>                    4     10    FB2_17  STD  RESET
clk_div<2>                    5     10    FB2_18  STD  RESET
$OpTx$$OpTx$FX_DC$43_INV$386  1     2     FB3_1   STD  
$OpTx$$OpTx$FX_DC$39_INV$385  1     2     FB3_2   STD  
$OpTx$$OpTx$FX_DC$37_INV$384  1     2     FB3_3   STD  
cnt_scan<0>                   2     2     FB3_4   STD  RESET

Signal                        Total Total Loc     Pwr  Reg Init
Name                          Pts   Inps          Mode State
clk_div<0>                    2     2     FB3_5   STD  RESET
$OpTx$FX_DC$63                2     4     FB3_6   STD  
$OpTx$FX_DC$58                2     3     FB3_7   STD  
$OpTx$FX_DC$47                2     3     FB3_8   STD  
$OpTx$FX_DC$40                2     3     FB3_9   STD  
$OpTx$$OpTx$FX_DC$68_INV$391  2     4     FB3_10  STD  
$OpTx$$OpTx$FX_DC$62_INV$390  2     4     FB3_11  STD  
$OpTx$$OpTx$FX_DC$61_INV$389  2     4     FB3_12  STD  
cnt_scan<2>                   3     4     FB3_13  STD  RESET
cnt_scan<1>                   3     3     FB3_14  STD  RESET
writeData_reg<3>              4     5     FB3_15  STD  RESET
writeData_reg<2>              4     5     FB3_16  STD  RESET
writeData_reg<1>              4     5     FB3_17  STD  RESET
writeData_reg<0>              4     5     FB3_18  STD  RESET
cnt_scan<7>                   3     9     FB4_4   STD  RESET
cnt_scan<6>                   3     8     FB4_5   STD  RESET
cnt_scan<5>                   3     7     FB4_6   STD  RESET
seg_data<7>_BUFR              12    14    FB4_8   STD  
cnt_scan<11>                  3     13    FB4_10  STD  RESET
seg_data<4>_BUFR              12    14    FB4_13  STD  
cnt_scan<10>                  3     12    FB4_14  STD  RESET
seg_data<2>_BUFR              12    14    FB4_16  STD  
cnt_scan<8>                   3     10    FB4_17  STD  RESET
cnt_scan<9>                   3     11    FB4_18  STD  RESET
$OpTx$$OpTx$FX_DC$53_INV$388  1     2     FB5_17  STD  
$OpTx$$OpTx$FX_DC$52_INV$387  1     2     FB5_18  STD  
$OpTx$FX_DC$69                4     7     FB6_1   STD  
readData_reg<1>               8     11    FB6_3   STD  RESET
inner_state_FFd2              11    12    FB6_7   STD  RESET
inner_state_FFd1              11    12    FB6_13  STD  RESET
inner_state_FFd3              14    13    FB6_16  STD  RESET
link                          25    14    FB7_4   STD  RESET
inner_state_FFd4              23    13    FB7_17  STD  RESET
readData_reg<6>               8     11    FB8_1   STD  RESET
i2c_state_FFd1                4     11    FB8_3   STD  RESET
i2c_state_FFd3                5     10    FB8_4   STD  RESET
i2c_state_FFd2                6     11    FB8_5   STD  RESET
readData_reg<7>               8     11    FB8_6   STD  RESET
readData_reg<5>               8     11    FB8_9   STD  RESET
readData_reg<4>               8     11    FB8_11  STD  RESET

Signal                        Total Total Loc     Pwr  Reg Init
Name                          Pts   Inps          Mode State
readData_reg<3>               8     11    FB8_12  STD  RESET
readData_reg<2>               8     11    FB8_13  STD  RESET
$OpTx$FX_DC$59                3     6     FB8_14  STD  
readData_reg<0>               8     11    FB8_15  STD  RESET

** 8 Inputs **

Signal                        Loc     Pin  Pin     Pin     
Name                                  No.  Type    Use     
clk                           FB4_5   128  I/O     I
data_in<1>                    FB5_7   66   I/O     I
data_in<3>                    FB5_14  61   I/O     I
data_in<2>                    FB5_15  64   I/O     I
data_in<0>                    FB5_17  69   I/O     I
rst                           FB7_2   71   I/O     I
rd_input                      FB8_11  98   I/O     I
wr_input                      FB8_12  100  I/O     I

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X            - Signal used as input to the macrocell logic.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               36/18
Number of signals used by logic mapping into function block:  36
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
cnt_delay<9>          4       0   /\1   0     FB1_1   23    I/O     (b)
cnt_delay<7>          4       0     0   1     FB1_2   16    I/O     (b)
cnt_delay<6>          4       0     0   1     FB1_3   17    I/O     (b)
cnt_delay<17>         4       0     0   1     FB1_4   25    I/O     (b)
cnt_delay<16>         4       0     0   1     FB1_5   19    I/O     (b)
cnt_delay<14>         4       0     0   1     FB1_6   20    I/O     (b)
cnt_delay<11>         4       0     0   1     FB1_7         (b)     (b)
cnt_delay<0>          4       0     0   1     FB1_8   21    I/O     (b)
start_delaycnt        5       0     0   0     FB1_9   22    I/O     (b)
cnt_delay<8>          5       0     0   0     FB1_10  31    I/O     (b)
cnt_delay<19>         5       0     0   0     FB1_11  24    I/O     (b)
cnt_delay<18>         5       0     0   0     FB1_12  26    I/O     (b)
cnt_delay<13>         5       0     0   0     FB1_13        (b)     (b)
cnt_delay<12>         5       0     0   0     FB1_14  27    I/O     (b)
cnt_delay<10>         5       0     0   0     FB1_15  28    I/O     (b)
main_state_FFd2       6       1<-   0   0     FB1_16  35    I/O     (b)
main_state_FFd1       6       2<- /\1   0     FB1_17  30    GCK/I/O (b)
cnt_delay<15>         4       1<- /\2   0     FB1_18        (b)     (b)

Signals Used by Logic in Function Block
  1: clk               13: cnt_delay<1>      25: inner_state_FFd1 
  2: cnt_delay<0>      14: cnt_delay<2>      26: inner_state_FFd3 
  3: cnt_delay<10>     15: cnt_delay<3>      27: inner_state_FFd4 
  4: cnt_delay<11>     16: cnt_delay<4>      28: main_state_FFd1 
  5: cnt_delay<12>     17: cnt_delay<5>      29: main_state_FFd2 
  6: cnt_delay<13>     18: cnt_delay<6>      30: phase1 
  7: cnt_delay<14>     19: cnt_delay<7>      31: phase3 
  8: cnt_delay<15>     20: cnt_delay<8>      32: rd_input 
  9: cnt_delay<16>     21: cnt_delay<9>      33: rst 
 10: cnt_delay<17>     22: i2c_state_FFd1    34: sda 
 11: cnt_delay<18>     23: i2c_state_FFd2    35: start_delaycnt 
 12: cnt_delay<19>     24: i2c_state_FFd3    36: wr_input