i2c.syr

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

HDL Synthesis Report

Macro Statistics
# FSMs                             : 3
# ROMs                             : 1
 16x8-bit ROM                      : 1
# Adders/Subtractors               : 2
 20-bit adder                      : 1
 8-bit adder                       : 1
# Counters                         : 1
 12-bit up counter                 : 1
# Registers                        : 29
 1-bit register                    : 25
 2-bit register                    : 1
 20-bit register                   : 1
 8-bit register                    : 2
# Multiplexers                     : 2
 1-bit 4-to-1 multiplexer          : 1
 8-bit 4-to-1 multiplexer          : 1
# Tristates                        : 1
 1-bit tristate buffer             : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch  <writeData_reg_7> (without init value) has a constant value of 0 in block <i2c>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <writeData_reg_6> (without init value) has a constant value of 0 in block <i2c>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <writeData_reg_4> (without init value) has a constant value of 0 in block <i2c>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <writeData_reg_5> (without init value) has a constant value of 0 in block <i2c>.

Optimizing unit <i2c> ...
Loading device for application Rf_Device from file 'v50.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block i2c, actual ratio is 20.
FlipFlop i2c_state_FFd1 has been replicated 2 time(s)
FlipFlop i2c_state_FFd2 has been replicated 2 time(s)
FlipFlop i2c_state_FFd3 has been replicated 2 time(s)
FlipFlop inner_state_FFd1 has been replicated 3 time(s)
FlipFlop inner_state_FFd3 has been replicated 3 time(s)
FlipFlop inner_state_FFd4 has been replicated 1 time(s)
FlipFlop main_state_FFd1 has been replicated 4 time(s)
FlipFlop main_state_FFd2 has been replicated 2 time(s)
FlipFlop phase3 has been replicated 3 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : i2c.ngr
Top Level Output File Name         : i2c
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 27

Macro Statistics :
# ROMs                             : 1
#      16x8-bit ROM                : 1
# Registers                        : 23
#      1-bit register              : 20
#      12-bit register             : 1
#      20-bit register             : 1
#      8-bit register              : 1
# Multiplexers                     : 2
#      1-bit 4-to-1 multiplexer    : 1
#      8-bit 4-to-1 multiplexer    : 1
# Tristates                        : 1
#      1-bit tristate buffer       : 1
# Adders/Subtractors               : 3
#      12-bit adder                : 1
#      20-bit adder                : 1
#      8-bit adder                 : 1

Cell Usage :
# BELS                             : 349
#      GND                         : 1
#      INV                         : 12
#      LUT1                        : 27
#      LUT1_L                      : 10
#      LUT2                        : 9
#      LUT2_D                      : 6
#      LUT2_L                      : 30
#      LUT3                        : 18
#      LUT3_D                      : 5
#      LUT3_L                      : 7
#      LUT4                        : 83
#      LUT4_D                      : 14
#      LUT4_L                      : 45
#      MUXCY                       : 37
#      MUXF5                       : 7
#      VCC                         : 1
#      XORCY                       : 37
# FlipFlops/Latches                : 93
#      FDC                         : 49
#      FDCE                        : 39
#      FDP                         : 2
#      FDPE                        : 3
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 26
#      IBUF                        : 7
#      IOBUF                       : 1
#      OBUF                        : 18
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-5 

 Number of Slices:                     139  out of    768    18%  
 Number of Slice Flip Flops:            93  out of   1536     6%  
 Number of 4 input LUTs:               254  out of   1536    16%  
 Number of bonded IOBs:                 27  out of     96    28%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 93    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 11.707ns (Maximum Frequency: 85.419MHz)
   Minimum input arrival time before clock: 10.282ns
   Maximum output required time after clock: 15.558ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 11.707ns (frequency: 85.419MHz)
  Total number of paths / destination ports: 2236 / 131
-------------------------------------------------------------------------
Delay:               11.707ns (Levels of Logic = 4)
  Source:            inner_state_FFd4 (FF)
  Destination:       sda_buf (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: inner_state_FFd4 to sda_buf
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             28   1.292   3.600  inner_state_FFd4 (inner_state_FFd4)
     LUT4:I3->O            1   0.653   1.150  _n0025354_SW0 (N1086)
     LUT4:I2->O            1   0.653   1.150  _n0025393_SW0 (N1095)
     LUT4:I3->O            1   0.653   1.150  _n0025421 (CHOICE211)
     LUT4_L:I3->LO         1   0.653   0.000  _n0025517 (_n0025)
     FDP:D                     0.753          sda_buf
    ----------------------------------------
    Total                     11.707ns (4.657ns logic, 7.050ns route)
                                       (39.8% logic, 60.2% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 27 / 16
-------------------------------------------------------------------------
Offset:              10.282ns (Levels of Logic = 6)
  Source:            sda (PAD)
  Destination:       sda_buf (FF)
  Destination Clock: clk rising

  Data Path: sda to sda_buf
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IOBUF:IO->O           2   0.924   1.340  sda_IOBUF (N1073)
     LUT3_D:I2->O          4   0.653   1.600  _n00561 (_n0056)
     LUT4:I0->O            1   0.653   1.150  _n002526 (CHOICE125)
     LUT4_L:I3->LO         1   0.653   0.100  _n002578 (CHOICE139)
     LUT4:I2->O            1   0.653   1.150  _n0025192 (CHOICE163)
     LUT4_L:I2->LO         1   0.653   0.000  _n0025517 (_n0025)
     FDP:D                     0.753          sda_buf
    ----------------------------------------
    Total                     10.282ns (4.942ns logic, 5.340ns route)
                                       (48.1% logic, 51.9% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 159 / 11
-------------------------------------------------------------------------
Offset:              15.558ns (Levels of Logic = 4)
  Source:            en_xhdl3_0 (FF)
  Destination:       seg_data<7> (PAD)
  Source Clock:      clk rising

  Data Path: en_xhdl3_0 to seg_data<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q            13   1.292   2.500  en_xhdl3_0 (en_xhdl3_0)
     LUT4:I0->O            7   0.653   1.950  seg_data_buf<3>1 (seg_data_buf<3>)
     LUT4:I3->O            1   0.653   1.150  Mrom__n0051_inst_lut4_71 (_n0051<7>)
     LUT4:I3->O            1   0.653   1.150  seg_data_xhdl4<7>2 (seg_data_7_OBUF)
     OBUF:I->O                 5.557          seg_data_7_OBUF (seg_data<7>)
    ----------------------------------------
    Total                     15.558ns (8.808ns logic, 6.750ns route)
                                       (56.6% logic, 43.4% route)

=========================================================================
CPU : 15.14 / 15.58 s | Elapsed : 15.00 / 16.00 s
 
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Total memory usage is 77828 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    7 (   0 filtered)
Number of infos    :    1 (   0 filtered)