📄 i2c.syr
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Release 7.1.04i - xst H.42Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.--> Parameter TMPDIR set to __projnavCPU : 0.00 / 0.39 s | Elapsed : 0.00 / 1.00 s --> Parameter xsthdpdir set to ./xstCPU : 0.00 / 0.39 s | Elapsed : 0.00 / 1.00 s --> Reading design: i2c.prjTABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) HDL Analysis 4) HDL Synthesis 5) Advanced HDL Synthesis 5.1) HDL Synthesis Report 6) Low Level Synthesis 7) Final Report 7.1) Device utilization summary 7.2) TIMING REPORT=========================================================================* Synthesis Options Summary *=========================================================================---- Source ParametersInput File Name : "i2c.prj"Input Format : mixedIgnore Synthesis Constraint File : NO---- Target ParametersOutput File Name : "i2c"Output Format : NGCTarget Device : xc2s50-5-TQ144---- Source OptionsTop Module Name : i2cAutomatic FSM Extraction : YESFSM Encoding Algorithm : AutoFSM Style : lutRAM Extraction : YesRAM Style : AutoROM Extraction : YesROM Style : AutoMux Extraction : YESMux Style : AutoDecoder Extraction : YESPriority Encoder Extraction : YESShift Register Extraction : YESLogical Shifter Extraction : YESXOR Collapsing : YESResource Sharing : YESMultiplier Style : lutAutomatic Register Balancing : No---- Target OptionsAdd IO Buffers : YESGlobal Maximum Fanout : 100Add Generic Clock Buffer(BUFG) : 4Register Duplication : YESEquivalent register Removal : YESSlice Packing : YESPack IO Registers into IOBs : auto---- General OptionsOptimization Goal : SpeedOptimization Effort : 1Keep Hierarchy : NOGlobal Optimization : AllClockNetsRTL Output : YesWrite Timing Constraints : NOHierarchy Separator : /Bus Delimiter : <>Case Specifier : maintainSlice Utilization Ratio : 100Slice Utilization Ratio Delta : 5---- Other Optionslso : i2c.lsoRead Cores : YEScross_clock_analysis : NOverilog2001 : YESsafe_implementation : NoOptimize Instantiated Primitives : NOtristate2logic : Yesuse_clock_enable : Yesuse_sync_set : Yesuse_sync_reset : Yesenable_auto_floorplanning : No==================================================================================================================================================* HDL Compilation *=========================================================================WARNING:HDLParsers:3215 - Unit work/I2C is now defined in a different file: was E:/temp/95144/vhdl/I2C/i2c.vhd, now is E:/temp/SPARTAN2/vhdl/Interface/I2C/i2c.vhdWARNING:HDLParsers:3215 - Unit work/I2C/TRANSLATED is now defined in a different file: was E:/temp/95144/vhdl/I2C/i2c.vhd, now is E:/temp/SPARTAN2/vhdl/Interface/I2C/i2c.vhdCompiling vhdl file "E:/temp/SPARTAN2/vhdl/Interface/I2C/i2c.vhd" in Library work.Architecture translated of Entity i2c is up to date.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <i2c> (Architecture <translated>).INFO:Xst:1304 - Contents of register <addr> in unit <i2c> never changes during circuit operation. The register is replaced by logic.Entity <i2c> analyzed. Unit <i2c> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <i2c>. Related source file is "E:/temp/SPARTAN2/vhdl/Interface/I2C/i2c.vhd".WARNING:Xst:646 - Signal <addr> is assigned but never used. Found finite state machine <FSM_0> for signal <inner_state>. ----------------------------------------------------------------------- | States | 11 | | Transitions | 184 | | Inputs | 11 | | Outputs | 11 | | Clock | clk (rising_edge) | | Reset | rst (negative) | | Reset type | asynchronous | | Reset State | 0000 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found finite state machine <FSM_1> for signal <main_state>. ----------------------------------------------------------------------- | States | 3 | | Transitions | 38 | | Inputs | 14 | | Outputs | 3 | | Clock | clk (rising_edge) | | Reset | rst (negative) | | Reset type | asynchronous | | Reset State | 00 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found finite state machine <FSM_2> for signal <i2c_state>. ----------------------------------------------------------------------- | States | 5 | | Transitions | 30 | | Inputs | 5 | | Outputs | 5 | | Clock | clk (rising_edge) | | Reset | rst (negative) | | Reset type | asynchronous | | Reset State | 000 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found 16x8-bit ROM for signal <$n0051>. Found 20-bit adder for signal <$n0049> created at line 91. Found 8-bit adder for signal <$n0050> created at line 110. Found 1-bit 4-to-1 multiplexer for signal <$n0053> created at line 418. Found 8-bit register for signal <clk_div>. Found 20-bit register for signal <cnt_delay>. Found 12-bit up counter for signal <cnt_scan>. Found 2-bit register for signal <en_xhdl3>. Found 1-bit register for signal <link>. Found 1-bit register for signal <phase0>. Found 1-bit register for signal <phase1>. Found 1-bit register for signal <phase2>. Found 1-bit register for signal <phase3>. Found 8-bit register for signal <readData_reg>. Found 1-bit register for signal <scl_xhdl1>. Found 1-bit register for signal <sda_buf>. Found 8-bit 4-to-1 multiplexer for signal <seg_data_buf>. Found 1-bit register for signal <start_delaycnt>. Found 1-bit tristate buffer for signal <temp_xhdl6>. Found 8-bit register for signal <writeData_reg>. Summary: inferred 3 Finite State Machine(s). inferred 1 ROM(s). inferred 1 Counter(s). inferred 44 D-type flip-flop(s). inferred 2 Adder/Subtractor(s). inferred 9 Multiplexer(s). inferred 1 Tristate(s).Unit <i2c> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Analyzing FSM <FSM_2> for best encoding.Optimizing FSM <FSM_2> on signal <i2c_state[1:3]> with sequential encoding.------------------- State | Encoding------------------- 000 | 000 001 | 001 010 | 010 011 | 100 100 | 011-------------------Analyzing FSM <FSM_1> for best encoding.Optimizing FSM <FSM_1> on signal <main_state[1:2]> with sequential encoding.------------------- State | Encoding------------------- 00 | 00 01 | 01 10 | 10-------------------Analyzing FSM <FSM_0> for best encoding.Optimizing FSM <FSM_0> on signal <inner_state[1:4]> with sequential encoding.------------------- State | Encoding------------------- 0000 | 0000 0001 | 0001 0010 | 0010 0011 | 0011 0100 | 0100 0101 | 0101 0110 | 0110 0111 | 0111 1000 | 1000 1001 | 1001 1010 | 1010-------------------Dynamic shift register inference ...=========================================================================⌨️ 快捷键说明
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