uart.mfd

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

;Imported pterms FB2_7
	# state_tras<2> & !state_tras<3> & key_entry2 & 
	!txd_buf<5> & div8_tras_reg<0> & txd_buf<6> & div8_tras_reg<1> & 
	div8_tras_reg<2>
	# state_tras<1> & !state_tras<3> & key_entry2 & 
	txd_buf<5> & div8_tras_reg<0> & !txd_buf<6> & div8_tras_reg<1> & 
	div8_tras_reg<2>
	# !state_tras<3> & state_tras<0> & key_entry2 & 
	!txd_buf<5> & div8_tras_reg<0> & txd_buf<6> & div8_tras_reg<1> & 
	div8_tras_reg<2>
;Imported pterms FB2_9
	# state_tras<1> & !state_tras<3> & key_entry2 & 
	!txd_buf<5> & div8_tras_reg<0> & txd_buf<6> & div8_tras_reg<1> & 
	div8_tras_reg<2>
	# !state_tras<2> & !state_tras<1> & state_tras<3> & 
	state_tras<0> & key_entry2 & txd_buf<5> & div8_tras_reg<0> & 
	div8_tras_reg<1> & div8_tras_reg<2>
	# !state_tras<2> & !state_tras<1> & state_tras<3> & 
	key_entry2 & txd_buf<5> & div8_tras_reg<0> & !txd_buf<6> & 
	div8_tras_reg<1> & div8_tras_reg<2>
	# state_tras<2> & state_tras<1> & state_tras<3> & 
	state_tras<0> & key_entry2 & !send_state<1> & !txd_buf<5> & 
	div8_tras_reg<0> & div8_tras_reg<1> & div8_tras_reg<2>
	# state_tras<2> & state_tras<1> & state_tras<3> & 
	state_tras<0> & key_entry2 & !send_state<2> & !txd_buf<5> & 
	div8_tras_reg<0> & div8_tras_reg<1> & div8_tras_reg<2>
;Imported pterms FB2_10
	# !state_tras<2> & !state_tras<1> & state_tras<3> & 
	!state_tras<0> & key_entry2 & !txd_buf<5> & div8_tras_reg<0> & 
	txd_buf<6> & div8_tras_reg<1> & div8_tras_reg<2>
	# state_tras<2> & state_tras<1> & state_tras<3> & 
	state_tras<0> & key_entry2 & send_state<1> & send_state<2> & 
	txd_buf<5> & div8_tras_reg<0> & div8_tras_reg<1> & 
	div8_tras_reg<2>;
   txd_buf<5>.CLK = clkbaud8x;
   txd_buf<5>.AR = !rst;

MACROCELL | 0 | 10 | cnt_delay<11>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 13 | 0 | 0 | 0 | 11 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 12 | 0 | 9 | 0 | 8 | 0 | 7 | 0 | 6 | 0 | 13 | 0 | 1
INPUTS | 14 | cnt_delay<0>  | cnt_delay<10>  | cnt_delay<8>  | cnt_delay<1>  | cnt_delay<2>  | cnt_delay<3>  | cnt_delay<4>  | cnt_delay<5>  | cnt_delay<6>  | cnt_delay<7>  | cnt_delay<9>  | clk  | rst  | start_delaycnt
INPUTMC | 12 | 0 | 11 | 0 | 17 | 0 | 12 | 2 | 17 | 2 | 16 | 2 | 15 | 2 | 14 | 0 | 5 | 0 | 4 | 0 | 3 | 0 | 2 | 0 | 0
INPUTP | 2 | 143 | 79
EQ | 6 | 
   cnt_delay<11>.T = cnt_delay<0> & cnt_delay<10> & cnt_delay<8> & 
	cnt_delay<1> & cnt_delay<2> & cnt_delay<3> & cnt_delay<4> & 
	cnt_delay<5> & cnt_delay<6> & cnt_delay<7> & cnt_delay<9>;
   cnt_delay<11>.CLK = clk;
   cnt_delay<11>.AR = !rst;
   cnt_delay<11>.CE = start_delaycnt;

MACROCELL | 0 | 9 | cnt_delay<14>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 12 | 0 | 0 | 0 | 11 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 12 | 0 | 8 | 0 | 7 | 0 | 6 | 0 | 13 | 0 | 1
INPUTS | 17 | cnt_delay<0>  | cnt_delay<10>  | cnt_delay<12>  | cnt_delay<13>  | cnt_delay<8>  | cnt_delay<11>  | cnt_delay<1>  | cnt_delay<2>  | cnt_delay<3>  | cnt_delay<4>  | cnt_delay<5>  | cnt_delay<6>  | cnt_delay<7>  | cnt_delay<9>  | clk  | rst  | start_delaycnt
INPUTMC | 15 | 0 | 11 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 12 | 0 | 10 | 2 | 17 | 2 | 16 | 2 | 15 | 2 | 14 | 0 | 5 | 0 | 4 | 0 | 3 | 0 | 2 | 0 | 0
INPUTP | 2 | 143 | 79
EQ | 7 | 
   cnt_delay<14>.T = cnt_delay<0> & cnt_delay<10> & cnt_delay<12> & 
	cnt_delay<13> & cnt_delay<8> & cnt_delay<11> & cnt_delay<1> & 
	cnt_delay<2> & cnt_delay<3> & cnt_delay<4> & cnt_delay<5> & 
	cnt_delay<6> & cnt_delay<7> & cnt_delay<9>;
   cnt_delay<14>.CLK = clk;
   cnt_delay<14>.AR = !rst;
   cnt_delay<14>.CE = start_delaycnt;

MACROCELL | 0 | 8 | cnt_delay<15>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 11 | 0 | 0 | 0 | 11 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 12 | 0 | 7 | 0 | 6 | 0 | 13 | 0 | 1
INPUTS | 18 | cnt_delay<0>  | cnt_delay<10>  | cnt_delay<12>  | cnt_delay<13>  | cnt_delay<8>  | cnt_delay<11>  | cnt_delay<14>  | cnt_delay<1>  | cnt_delay<2>  | cnt_delay<3>  | cnt_delay<4>  | cnt_delay<5>  | cnt_delay<6>  | cnt_delay<7>  | cnt_delay<9>  | clk  | rst  | start_delaycnt
INPUTMC | 16 | 0 | 11 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 12 | 0 | 10 | 0 | 9 | 2 | 17 | 2 | 16 | 2 | 15 | 2 | 14 | 0 | 5 | 0 | 4 | 0 | 3 | 0 | 2 | 0 | 0
INPUTP | 2 | 143 | 79
EQ | 7 | 
   cnt_delay<15>.T = cnt_delay<0> & cnt_delay<10> & cnt_delay<12> & 
	cnt_delay<13> & cnt_delay<8> & cnt_delay<11> & cnt_delay<14> & 
	cnt_delay<1> & cnt_delay<2> & cnt_delay<3> & cnt_delay<4> & 
	cnt_delay<5> & cnt_delay<6> & cnt_delay<7> & cnt_delay<9>;
   cnt_delay<15>.CLK = clk;
   cnt_delay<15>.AR = !rst;
   cnt_delay<15>.CE = start_delaycnt;

MACROCELL | 0 | 7 | cnt_delay<16>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 10 | 0 | 0 | 0 | 11 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 12 | 0 | 6 | 0 | 13 | 0 | 1
INPUTS | 19 | cnt_delay<0>  | cnt_delay<10>  | cnt_delay<12>  | cnt_delay<13>  | cnt_delay<8>  | cnt_delay<11>  | cnt_delay<14>  | cnt_delay<15>  | cnt_delay<1>  | cnt_delay<2>  | cnt_delay<3>  | cnt_delay<4>  | cnt_delay<5>  | cnt_delay<6>  | cnt_delay<7>  | cnt_delay<9>  | clk  | rst  | start_delaycnt
INPUTMC | 17 | 0 | 11 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 12 | 0 | 10 | 0 | 9 | 0 | 8 | 2 | 17 | 2 | 16 | 2 | 15 | 2 | 14 | 0 | 5 | 0 | 4 | 0 | 3 | 0 | 2 | 0 | 0
INPUTP | 2 | 143 | 79
EQ | 8 | 
   cnt_delay<16>.T = cnt_delay<0> & cnt_delay<10> & cnt_delay<12> & 
	cnt_delay<13> & cnt_delay<8> & cnt_delay<11> & cnt_delay<14> & 
	cnt_delay<15> & cnt_delay<1> & cnt_delay<2> & cnt_delay<3> & 
	cnt_delay<4> & cnt_delay<5> & cnt_delay<6> & cnt_delay<7> & 
	cnt_delay<9>;
   cnt_delay<16>.CLK = clk;
   cnt_delay<16>.AR = !rst;
   cnt_delay<16>.CE = start_delaycnt;

MACROCELL | 0 | 6 | cnt_delay<17>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 9 | 0 | 0 | 0 | 11 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 12 | 0 | 13 | 0 | 1
INPUTS | 20 | cnt_delay<0>  | cnt_delay<10>  | cnt_delay<12>  | cnt_delay<13>  | cnt_delay<8>  | cnt_delay<11>  | cnt_delay<14>  | cnt_delay<15>  | cnt_delay<16>  | cnt_delay<1>  | cnt_delay<2>  | cnt_delay<3>  | cnt_delay<4>  | cnt_delay<5>  | cnt_delay<6>  | cnt_delay<7>  | cnt_delay<9>  | clk  | rst  | start_delaycnt
INPUTMC | 18 | 0 | 11 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 12 | 0 | 10 | 0 | 9 | 0 | 8 | 0 | 7 | 2 | 17 | 2 | 16 | 2 | 15 | 2 | 14 | 0 | 5 | 0 | 4 | 0 | 3 | 0 | 2 | 0 | 0
INPUTP | 2 | 143 | 79
EQ | 8 | 
   cnt_delay<17>.T = cnt_delay<0> & cnt_delay<10> & cnt_delay<12> & 
	cnt_delay<13> & cnt_delay<8> & cnt_delay<11> & cnt_delay<14> & 
	cnt_delay<15> & cnt_delay<16> & cnt_delay<1> & cnt_delay<2> & 
	cnt_delay<3> & cnt_delay<4> & cnt_delay<5> & cnt_delay<6> & 
	cnt_delay<7> & cnt_delay<9>;
   cnt_delay<17>.CLK = clk;
   cnt_delay<17>.AR = !rst;
   cnt_delay<17>.CE = start_delaycnt;

MACROCELL | 0 | 13 | cnt_delay<19>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 9 | 0 | 0 | 0 | 11 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 12 | 0 | 13 | 0 | 1
INPUTS | 23 | cnt_delay<0>  | cnt_delay<10>  | cnt_delay<12>  | cnt_delay<13>  | cnt_delay<18>  | cnt_delay<8>  | cnt_delay<11>  | cnt_delay<14>  | cnt_delay<15>  | cnt_delay<16>  | cnt_delay<17>  | cnt_delay<1>  | cnt_delay<2>  | cnt_delay<3>  | cnt_delay<4>  | cnt_delay<5>  | cnt_delay<6>  | cnt_delay<7>  | cnt_delay<9>  | cnt_delay<19>  | clk  | rst  | start_delaycnt
INPUTMC | 21 | 0 | 11 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 12 | 0 | 10 | 0 | 9 | 0 | 8 | 0 | 7 | 0 | 6 | 2 | 17 | 2 | 16 | 2 | 15 | 2 | 14 | 0 | 5 | 0 | 4 | 0 | 3 | 0 | 2 | 0 | 13 | 0 | 0
INPUTP | 2 | 143 | 79
EQ | 14 | 
   cnt_delay<19>.T = cnt_delay<0> & cnt_delay<10> & cnt_delay<12> & 
	cnt_delay<13> & cnt_delay<18> & cnt_delay<8> & cnt_delay<11> & 
	cnt_delay<14> & cnt_delay<15> & cnt_delay<16> & cnt_delay<17> & 
	cnt_delay<1> & cnt_delay<2> & cnt_delay<3> & cnt_delay<4> & 
	cnt_delay<5> & cnt_delay<6> & cnt_delay<7> & cnt_delay<9>
	# !cnt_delay<0> & cnt_delay<10> & cnt_delay<12> & 
	cnt_delay<13> & cnt_delay<18> & cnt_delay<8> & !cnt_delay<11> & 
	!cnt_delay<14> & !cnt_delay<15> & !cnt_delay<16> & !cnt_delay<17> & 
	cnt_delay<19> & !cnt_delay<1> & !cnt_delay<2> & !cnt_delay<3> & 
	!cnt_delay<4> & !cnt_delay<5> & !cnt_delay<6> & !cnt_delay<7> & 
	!cnt_delay<9>;
   cnt_delay<19>.CLK = clk;
   cnt_delay<19>.AR = !rst;
   cnt_delay<19>.CE = start_delaycnt;

MACROCELL | 2 | 17 | cnt_delay<1>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 21 | 0 | 0 | 0 | 11 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 12 | 0 | 10 | 0 | 9 | 0 | 8 | 0 | 7 | 0 | 6 | 0 | 13 | 2 | 16 | 2 | 15 | 2 | 14 | 0 | 5 | 0 | 4 | 0 | 3 | 0 | 2 | 0 | 1
INPUTS | 4 | cnt_delay<0>  | clk  | rst  | start_delaycnt
INPUTMC | 2 | 0 | 11 | 0 | 0
INPUTP | 2 | 143 | 79
EQ | 4 | 
   cnt_delay<1>.T = cnt_delay<0>;
   cnt_delay<1>.CLK = clk;
   cnt_delay<1>.AR = !rst;
   cnt_delay<1>.CE = start_delaycnt;

MACROCELL | 2 | 16 | cnt_delay<2>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 20 | 0 | 0 | 0 | 11 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 12 | 0 | 10 | 0 | 9 | 0 | 8 | 0 | 7 | 0 | 6 | 0 | 13 | 2 | 15 | 2 | 14 | 0 | 5 | 0 | 4 | 0 | 3 | 0 | 2 | 0 | 1
INPUTS | 5 | cnt_delay<0>  | cnt_delay<1>  | clk  | rst  | start_delaycnt
INPUTMC | 3 | 0 | 11 | 2 | 17 | 0 | 0
INPUTP | 2 | 143 | 79
EQ | 4 | 
   cnt_delay<2>.T = cnt_delay<0> & cnt_delay<1>;
   cnt_delay<2>.CLK = clk;
   cnt_delay<2>.AR = !rst;
   cnt_delay<2>.CE = start_delaycnt;

MACROCELL | 2 | 15 | cnt_delay<3>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 19 | 0 | 0 | 0 | 11 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 12 | 0 | 10 | 0 | 9 | 0 | 8 | 0 | 7 | 0 | 6 | 0 | 13 | 2 | 14 | 0 | 5 | 0 | 4 | 0 | 3 | 0 | 2 | 0 | 1
INPUTS | 6 | cnt_delay<0>  | cnt_delay<1>  | cnt_delay<2>  | clk  | rst  | start_delaycnt
INPUTMC | 4 | 0 | 11 | 2 | 17 | 2 | 16 | 0 | 0
INPUTP | 2 | 143 | 79
EQ | 4 | 
   cnt_delay<3>.T = cnt_delay<0> & cnt_delay<1> & cnt_delay<2>;
   cnt_delay<3>.CLK = clk;
   cnt_delay<3>.AR = !rst;
   cnt_delay<3>.CE = start_delaycnt;

MACROCELL | 2 | 14 | cnt_delay<4>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 18 | 0 | 0 | 0 | 11 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 12 | 0 | 10 | 0 | 9 | 0 | 8 | 0 | 7 | 0 | 6 | 0 | 13 | 0 | 5 | 0 | 4 | 0 | 3 | 0 | 2 | 0 | 1
INPUTS | 7 | cnt_delay<0>  | cnt_delay<1>  | cnt_delay<2>  | cnt_delay<3>  | clk  | rst  | start_delaycnt
INPUTMC | 5 | 0 | 11 | 2 | 17 | 2 | 16 | 2 | 15 | 0 | 0
INPUTP | 2 | 143 | 79
EQ | 5 | 
   cnt_delay<4>.T = cnt_delay<0> & cnt_delay<1> & cnt_delay<2> & 
	cnt_delay<3>;
   cnt_delay<4>.CLK = clk;
   cnt_delay<4>.AR = !rst;
   cnt_delay<4>.CE = start_delaycnt;

MACROCELL | 0 | 5 | cnt_delay<5>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 17 | 0 | 0 | 0 | 11 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 12 | 0 | 10 | 0 | 9 | 0 | 8 | 0 | 7 | 0 | 6 | 0 | 13 | 0 | 4 | 0 | 3 | 0 | 2 | 0 | 1
INPUTS | 8 | cnt_delay<0>  | cnt_delay<1>  | cnt_delay<2>  | cnt_delay<3>  | cnt_delay<4>  | clk  | rst  | start_delaycnt
INPUTMC | 6 | 0 | 11 | 2 | 17 | 2 | 16 | 2 | 15 | 2 | 14 | 0 | 0
INPUTP | 2 | 143 | 79
EQ | 5 | 
   cnt_delay<5>.T = cnt_delay<0> & cnt_delay<1> & cnt_delay<2> & 
	cnt_delay<3> & cnt_delay<4>;
   cnt_delay<5>.CLK = clk;
   cnt_delay<5>.AR = !rst;
   cnt_delay<5>.CE = start_delaycnt;

MACROCELL | 0 | 4 | cnt_delay<6>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 16 | 0 | 0 | 0 | 11 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 12 | 0 | 10 | 0 | 9 | 0 | 8 | 0 | 7 | 0 | 6 | 0 | 13 | 0 | 3 | 0 | 2 | 0 | 1
INPUTS | 9 | cnt_delay<0>  | cnt_delay<1>  | cnt_delay<2>  | cnt_delay<3>  | cnt_delay<4>  | cnt_delay<5>  | clk  | rst  | start_delaycnt
INPUTMC | 7 | 0 | 11 | 2 | 17 | 2 | 16 | 2 | 15 | 2 | 14 | 0 | 5 | 0 | 0
INPUTP | 2 | 143 | 79
EQ | 5 | 
   cnt_delay<6>.T = cnt_delay<0> & cnt_delay<1> & cnt_delay<2> & 
	cnt_delay<3> & cnt_delay<4> & cnt_delay<5>;
   cnt_delay<6>.CLK = clk;
   cnt_delay<6>.AR = !rst;
   cnt_delay<6>.CE = start_delaycnt;

MACROCELL | 0 | 3 | cnt_delay<7>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 15 | 0 | 0 | 0 | 11 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 12 | 0 | 10 | 0 | 9 | 0 | 8 | 0 | 7 | 0 | 6 | 0 | 13 | 0 | 2 | 0 | 1
INPUTS | 10 | cnt_delay<0>  | cnt_delay<1>  | cnt_delay<2>  | cnt_delay<3>  | cnt_delay<4>  | cnt_delay<5>  | cnt_delay<6>  | clk  | rst  | start_delaycnt
INPUTMC | 8 | 0 | 11 | 2 | 17 | 2 | 16 | 2 | 15 | 2 | 14 | 0 | 5 | 0 | 4 | 0 | 0
INPUTP | 2 | 143 | 79
EQ | 5 | 
   cnt_delay<7>.T = cnt_delay<0> & cnt_delay<1> & cnt_delay<2> & 
	cnt_delay<3> & cnt_delay<4> & cnt_delay<5> & cnt_delay<6>;
   cnt_delay<7>.CLK = clk;
   cnt_delay<7>.AR = !rst;
   cnt_delay<7>.CE = start_delaycnt;

MACROCELL | 0 | 2 | cnt_delay<9>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 14 | 0 | 0 | 0 | 11 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 12 | 0 | 10 | 0 | 9 | 0 | 8 | 0 | 7 | 0 | 6 | 0 | 13 | 0 | 1
INPUTS | 12 | cnt_delay<0>  | cnt_delay<8>  | cnt_delay<1>  | cnt_delay<2>  | cnt_delay<3>  | cnt_delay<4>  | cnt_delay<5>  | cnt_delay<6>  | cnt_delay<7>  | clk  | rst  | start_delaycnt
INPUTMC | 10 | 0 | 11 | 0 | 12 | 2 | 17 | 2 | 16 | 2 | 15 | 2 | 14 | 0 | 5 | 0 | 4 | 0 | 3 | 0 | 0
INPUTP | 2 | 143 | 79
EQ | 6 | 
   cnt_delay<9>.T = cnt_delay<0> & cnt_delay<8> & cnt_delay<1> & 
	cnt_delay<2> & cnt_delay<3> & cnt_delay<4> & cnt_delay<5> & 
	cnt_delay<6> & cnt_delay<7>;
   cnt_delay<9>.CLK = clk;
   cnt_delay<9>.AR = !rst;
   cnt_delay<9>.CE = start_delaycnt;

MACROCELL | 2 | 13 | div8_rec_reg<0>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 25 | 3 | 13 | 3 | 7 | 3 | 6 | 3 | 4 | 3