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📁 Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档
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MACROCELL | 0 | 15 | cnt_delay<13>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 13 | 0 | 0 | 0 | 11 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 12 | 0 | 9 | 0 | 8 | 0 | 7 | 0 | 6 | 0 | 13 | 0 | 1
INPUTS | 23 | cnt_delay<0>  | cnt_delay<10>  | cnt_delay<12>  | cnt_delay<8>  | cnt_delay<11>  | cnt_delay<1>  | cnt_delay<2>  | cnt_delay<3>  | cnt_delay<4>  | cnt_delay<5>  | cnt_delay<6>  | cnt_delay<7>  | cnt_delay<9>  | cnt_delay<13>  | cnt_delay<18>  | cnt_delay<14>  | cnt_delay<15>  | cnt_delay<16>  | cnt_delay<17>  | cnt_delay<19>  | clk  | rst  | start_delaycnt
INPUTMC | 21 | 0 | 11 | 0 | 17 | 0 | 16 | 0 | 12 | 0 | 10 | 2 | 17 | 2 | 16 | 2 | 15 | 2 | 14 | 0 | 5 | 0 | 4 | 0 | 3 | 0 | 2 | 0 | 15 | 0 | 14 | 0 | 9 | 0 | 8 | 0 | 7 | 0 | 6 | 0 | 13 | 0 | 0
INPUTP | 2 | 143 | 79
EQ | 13 | 
   cnt_delay<13>.T = cnt_delay<0> & cnt_delay<10> & cnt_delay<12> & 
	cnt_delay<8> & cnt_delay<11> & cnt_delay<1> & cnt_delay<2> & 
	cnt_delay<3> & cnt_delay<4> & cnt_delay<5> & cnt_delay<6> & 
	cnt_delay<7> & cnt_delay<9>
	# !cnt_delay<0> & cnt_delay<10> & cnt_delay<12> & 
	cnt_delay<13> & cnt_delay<18> & cnt_delay<8> & !cnt_delay<11> & 
	!cnt_delay<14> & !cnt_delay<15> & !cnt_delay<16> & !cnt_delay<17> & 
	cnt_delay<19> & !cnt_delay<1> & !cnt_delay<2> & !cnt_delay<3> & 
	!cnt_delay<4> & !cnt_delay<5> & !cnt_delay<6> & !cnt_delay<7> & 
	!cnt_delay<9>;
   cnt_delay<13>.CLK = clk;
   cnt_delay<13>.AR = !rst;
   cnt_delay<13>.CE = start_delaycnt;

MACROCELL | 0 | 14 | cnt_delay<18>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 9 | 0 | 0 | 0 | 11 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 12 | 0 | 13 | 0 | 1
INPUTS | 23 | cnt_delay<0>  | cnt_delay<10>  | cnt_delay<12>  | cnt_delay<13>  | cnt_delay<8>  | cnt_delay<11>  | cnt_delay<14>  | cnt_delay<15>  | cnt_delay<16>  | cnt_delay<17>  | cnt_delay<1>  | cnt_delay<2>  | cnt_delay<3>  | cnt_delay<4>  | cnt_delay<5>  | cnt_delay<6>  | cnt_delay<7>  | cnt_delay<9>  | cnt_delay<18>  | cnt_delay<19>  | clk  | rst  | start_delaycnt
INPUTMC | 21 | 0 | 11 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 12 | 0 | 10 | 0 | 9 | 0 | 8 | 0 | 7 | 0 | 6 | 2 | 17 | 2 | 16 | 2 | 15 | 2 | 14 | 0 | 5 | 0 | 4 | 0 | 3 | 0 | 2 | 0 | 14 | 0 | 13 | 0 | 0
INPUTP | 2 | 143 | 79
EQ | 14 | 
   cnt_delay<18>.T = cnt_delay<0> & cnt_delay<10> & cnt_delay<12> & 
	cnt_delay<13> & cnt_delay<8> & cnt_delay<11> & cnt_delay<14> & 
	cnt_delay<15> & cnt_delay<16> & cnt_delay<17> & cnt_delay<1> & 
	cnt_delay<2> & cnt_delay<3> & cnt_delay<4> & cnt_delay<5> & 
	cnt_delay<6> & cnt_delay<7> & cnt_delay<9>
	# !cnt_delay<0> & cnt_delay<10> & cnt_delay<12> & 
	cnt_delay<13> & cnt_delay<18> & cnt_delay<8> & !cnt_delay<11> & 
	!cnt_delay<14> & !cnt_delay<15> & !cnt_delay<16> & !cnt_delay<17> & 
	cnt_delay<19> & !cnt_delay<1> & !cnt_delay<2> & !cnt_delay<3> & 
	!cnt_delay<4> & !cnt_delay<5> & !cnt_delay<6> & !cnt_delay<7> & 
	!cnt_delay<9>;
   cnt_delay<18>.CLK = clk;
   cnt_delay<18>.AR = !rst;
   cnt_delay<18>.CE = start_delaycnt;

MACROCELL | 0 | 12 | cnt_delay<8>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 15 | 0 | 0 | 0 | 11 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 12 | 0 | 10 | 0 | 9 | 0 | 8 | 0 | 7 | 0 | 6 | 0 | 13 | 0 | 2 | 0 | 1
INPUTS | 23 | cnt_delay<0>  | cnt_delay<1>  | cnt_delay<2>  | cnt_delay<3>  | cnt_delay<4>  | cnt_delay<5>  | cnt_delay<6>  | cnt_delay<7>  | cnt_delay<10>  | cnt_delay<12>  | cnt_delay<13>  | cnt_delay<18>  | cnt_delay<8>  | cnt_delay<11>  | cnt_delay<14>  | cnt_delay<15>  | cnt_delay<16>  | cnt_delay<17>  | cnt_delay<19>  | cnt_delay<9>  | clk  | rst  | start_delaycnt
INPUTMC | 21 | 0 | 11 | 2 | 17 | 2 | 16 | 2 | 15 | 2 | 14 | 0 | 5 | 0 | 4 | 0 | 3 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 12 | 0 | 10 | 0 | 9 | 0 | 8 | 0 | 7 | 0 | 6 | 0 | 13 | 0 | 2 | 0 | 0
INPUTP | 2 | 143 | 79
EQ | 12 | 
   cnt_delay<8>.T = cnt_delay<0> & cnt_delay<1> & cnt_delay<2> & 
	cnt_delay<3> & cnt_delay<4> & cnt_delay<5> & cnt_delay<6> & 
	cnt_delay<7>
	# !cnt_delay<0> & cnt_delay<10> & cnt_delay<12> & 
	cnt_delay<13> & cnt_delay<18> & cnt_delay<8> & !cnt_delay<11> & 
	!cnt_delay<14> & !cnt_delay<15> & !cnt_delay<16> & !cnt_delay<17> & 
	cnt_delay<19> & !cnt_delay<1> & !cnt_delay<2> & !cnt_delay<3> & 
	!cnt_delay<4> & !cnt_delay<5> & !cnt_delay<6> & !cnt_delay<7> & 
	!cnt_delay<9>;
   cnt_delay<8>.CLK = clk;
   cnt_delay<8>.AR = !rst;
   cnt_delay<8>.CE = start_delaycnt;

MACROCELL | 5 | 4 | state_rec<3>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 24 | 3 | 13 | 3 | 7 | 3 | 6 | 3 | 4 | 3 | 17 | 3 | 15 | 3 | 9 | 5 | 17 | 5 | 15 | 5 | 2 | 5 | 0 | 5 | 4 | 5 | 5 | 5 | 6 | 3 | 2 | 3 | 3 | 3 | 5 | 3 | 8 | 3 | 10 | 3 | 12 | 3 | 14 | 3 | 16 | 5 | 14 | 5 | 16
INPUTS | 9 | state_rec<0>  | state_rec<1>  | state_rec<2>  | state_rec<3>  | div8_rec_reg<0>  | div8_rec_reg<1>  | div8_rec_reg<2>  | clkbaud8x  | rst
INPUTMC | 8 | 5 | 15 | 5 | 2 | 5 | 0 | 5 | 4 | 2 | 13 | 5 | 13 | 5 | 12 | 7 | 14
INPUTP | 1 | 79
EQ | 8 | 
   state_rec<3>.T = state_rec<0> & state_rec<1> & state_rec<2> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
	# state_rec<0> & !state_rec<1> & !state_rec<2> & 
	state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>;
   state_rec<3>.CLK = clkbaud8x;
   state_rec<3>.AR = !rst;

MACROCELL | 6 | 12 | txd_buf<2>
ATTRIBUTES | 8520496 | 0
OUTPUTMC | 7 | 6 | 12 | 6 | 2 | 6 | 0 | 6 | 1 | 6 | 10 | 6 | 11 | 6 | 13
INPUTS | 15 | state_tras<1>  | state_tras<3>  | state_tras<0>  | key_entry2  | txd_buf<2>  | div8_tras_reg<0>  | state_tras<2>  | send_state<1>  | send_state<2>  | send_state<0>  | div8_tras_reg<1>  | div8_tras_reg<2>  | EXP27_.EXP  | clkbaud8x  | rst
INPUTMC | 14 | 1 | 2 | 1 | 6 | 1 | 15 | 1 | 10 | 6 | 12 | 1 | 4 | 1 | 11 | 1 | 9 | 1 | 5 | 1 | 3 | 1 | 13 | 1 | 12 | 6 | 11 | 7 | 14
INPUTP | 1 | 79
EXPORTS | 1 | 6 | 13
IMPORTS | 1 | 6 | 11
EQ | 39 | 
   !txd_buf<2>.D = key_entry2 & !txd_buf<2> & !div8_tras_reg<0>
	# state_tras<1> & state_tras<3> & !state_tras<0> & 
	key_entry2 & !txd_buf<2>
;Imported pterms FB7_12
	# key_entry2 & !txd_buf<2> & !div8_tras_reg<1>
	# key_entry2 & !txd_buf<2> & !div8_tras_reg<2>
	# !key_entry2 & !txd_buf<2> & !key_entry1
	# state_tras<2> & !state_tras<1> & state_tras<3> & 
	key_entry2 & !txd_buf<2>
	# !state_tras<2> & state_tras<1> & state_tras<3> & 
	key_entry2 & !txd_buf<2>
;Imported pterms FB7_11
	# !state_tras<2> & !state_tras<1> & !state_tras<3> & 
	!state_tras<0> & key_entry2 & !txd_buf<2>
	# state_tras<2> & !state_tras<3> & key_entry2 & 
	!txd_buf<3> & div8_tras_reg<0> & div8_tras_reg<1> & 
	div8_tras_reg<2>
	# state_tras<1> & !state_tras<3> & key_entry2 & 
	!txd_buf<3> & div8_tras_reg<0> & div8_tras_reg<1> & 
	div8_tras_reg<2>
	# !state_tras<3> & state_tras<0> & key_entry2 & 
	!txd_buf<3> & div8_tras_reg<0> & div8_tras_reg<1> & 
	div8_tras_reg<2>
	# !state_tras<2> & !state_tras<1> & state_tras<3> & 
	!state_tras<0> & key_entry2 & !txd_buf<3> & div8_tras_reg<0> & 
	div8_tras_reg<1> & div8_tras_reg<2>
;Imported pterms FB7_10
	# state_tras<2> & state_tras<1> & state_tras<3> & 
	state_tras<0> & key_entry2 & send_state<1> & send_state<2> & 
	div8_tras_reg<0> & div8_tras_reg<1> & div8_tras_reg<2>
	# state_tras<2> & state_tras<1> & state_tras<3> & 
	state_tras<0> & key_entry2 & send_state<1> & !send_state<0> & 
	div8_tras_reg<0> & div8_tras_reg<1> & div8_tras_reg<2>;
   txd_buf<2>.CLK = clkbaud8x;
   txd_buf<2>.AR = !rst;
    txd_buf<2>.EXP  =  state_tras<2> & state_tras<1> & state_tras<3> & 
	state_tras<0> & key_entry2 & !send_state<1> & !send_state<2> & 
	send_state<0> & div8_tras_reg<0> & div8_tras_reg<1> & 
	div8_tras_reg<2>

MACROCELL | 6 | 6 | txd_buf<3>
ATTRIBUTES | 8520496 | 0
OUTPUTMC | 5 | 6 | 10 | 6 | 6 | 6 | 4 | 6 | 5 | 6 | 7
INPUTS | 17 | key_entry2  | txd_buf<3>  | div8_tras_reg<0>  | state_tras<2>  | state_tras<1>  | state_tras<3>  | txd_buf<0>  | div8_tras_reg<1>  | div8_tras_reg<2>  | txd  | state_tras<0>  | send_state<1>  | send_state<2>  | send_state<0>  | clkbaud8x  | rst  | EXP23_.EXP
INPUTMC | 16 | 1 | 10 | 6 | 6 | 1 | 4 | 1 | 11 | 1 | 2 | 1 | 6 | 6 | 14 | 1 | 13 | 1 | 12 | 6 | 9 | 1 | 15 | 1 | 9 | 1 | 5 | 1 | 3 | 7 | 14 | 6 | 5
INPUTP | 1 | 79
EXPORTS | 1 | 6 | 7
IMPORTS | 1 | 6 | 5
EQ | 42 | 
   txd_buf<3>.D = key_entry2 & txd_buf<3> & !div8_tras_reg<0>
;Imported pterms FB7_6
	# key_entry2 & txd_buf<3> & !div8_tras_reg<1>
	# key_entry2 & txd_buf<3> & !div8_tras_reg<2>
	# !key_entry2 & txd_buf<3> & !key_entry1
	# state_tras<2> & !state_tras<1> & state_tras<3> & 
	key_entry2 & txd_buf<3>
	# !state_tras<2> & state_tras<1> & state_tras<3> & 
	key_entry2 & txd_buf<3>
;Imported pterms FB7_5
	# state_tras<2> & state_tras<3> & !state_tras<0> & 
	key_entry2 & txd_buf<3>
	# !state_tras<2> & !state_tras<1> & !state_tras<3> & 
	!state_tras<0> & key_entry2 & txd_buf<3>
	# state_tras<2> & !state_tras<3> & key_entry2 & 
	txd_buf<4> & div8_tras_reg<0> & div8_tras_reg<1> & 
	div8_tras_reg<2>
	# state_tras<1> & !state_tras<3> & key_entry2 & 
	txd_buf<4> & div8_tras_reg<0> & div8_tras_reg<1> & 
	div8_tras_reg<2>
	# !state_tras<3> & state_tras<0> & key_entry2 & 
	txd_buf<4> & div8_tras_reg<0> & div8_tras_reg<1> & 
	div8_tras_reg<2>
;Imported pterms FB7_4
	# !state_tras<2> & !state_tras<1> & state_tras<3> & 
	!state_tras<0> & key_entry2 & txd_buf<4> & div8_tras_reg<0> & 
	div8_tras_reg<1> & div8_tras_reg<2>
	# state_tras<2> & state_tras<1> & state_tras<3> & 
	state_tras<0> & key_entry2 & !send_state<2> & send_state<0> & 
	div8_tras_reg<0> & div8_tras_reg<1> & div8_tras_reg<2>
	# state_tras<2> & state_tras<1> & state_tras<3> & 
	state_tras<0> & key_entry2 & !send_state<1> & send_state<2> & 
	!send_state<0> & div8_tras_reg<0> & div8_tras_reg<1> & 
	div8_tras_reg<2>;
   txd_buf<3>.CLK = clkbaud8x;
   txd_buf<3>.AR = !rst;
    txd_buf<3>.EXP  =  !state_tras<2> & !state_tras<1> & state_tras<3> & 
	txd_buf<0> & div8_tras_reg<0> & div8_tras_reg<1> & 
	div8_tras_reg<2>
	# txd & !state_tras<2> & !state_tras<1> & 
	!state_tras<3> & !state_tras<0> & send_state<1> & send_state<2> & 
	send_state<0>

MACROCELL | 1 | 1 | txd_buf<4>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 6 | 6 | 4 | 1 | 1 | 1 | 0 | 1 | 2 | 1 | 17 | 6 | 3
INPUTS | 14 | key_entry2  | txd_buf<4>  | key_entry1  | state_tras<2>  | state_tras<3>  | txd_buf<5>  | div8_tras_reg<0>  | div8_tras_reg<1>  | div8_tras_reg<2>  | state_tras<1>  | EXP10_.EXP  | clkbaud8x  | rst  | state_tras<1>.EXP
INPUTMC | 13 | 1 | 10 | 1 | 1 | 0 | 1 | 1 | 11 | 1 | 6 | 1 | 7 | 1 | 4 | 1 | 13 | 1 | 12 | 1 | 2 | 1 | 0 | 7 | 14 | 1 | 2
INPUTP | 1 | 79
IMPORTS | 2 | 1 | 0 | 1 | 2
EQ | 36 | 
   txd_buf<4>.T = !key_entry2 & !txd_buf<4> & key_entry1
	# state_tras<2> & !state_tras<3> & key_entry2 & 
	txd_buf<4> & !txd_buf<5> & div8_tras_reg<0> & div8_tras_reg<1> & 
	div8_tras_reg<2>
	# state_tras<1> & !state_tras<3> & key_entry2 & 
	txd_buf<4> & !txd_buf<5> & div8_tras_reg<0> & div8_tras_reg<1> & 
	div8_tras_reg<2>
;Imported pterms FB2_1
	# state_tras<2> & !state_tras<3> & key_entry2 & 
	!txd_buf<4> & txd_buf<5> & div8_tras_reg<0> & div8_tras_reg<1> & 
	div8_tras_reg<2>
	# state_tras<1> & !state_tras<3> & key_entry2 & 
	!txd_buf<4> & txd_buf<5> & div8_tras_reg<0> & div8_tras_reg<1> & 
	div8_tras_reg<2>
	# !state_tras<3> & state_tras<0> & key_entry2 & 
	txd_buf<4> & !txd_buf<5> & div8_tras_reg<0> & div8_tras_reg<1> & 
	div8_tras_reg<2>
	# !state_tras<3> & state_tras<0> & key_entry2 & 
	!txd_buf<4> & txd_buf<5> & div8_tras_reg<0> & div8_tras_reg<1> & 
	div8_tras_reg<2>
	# state_tras<2> & state_tras<1> & state_tras<3> & 
	state_tras<0> & key_entry2 & txd_buf<4> & div8_tras_reg<0> & 
	div8_tras_reg<1> & div8_tras_reg<2>
;Imported pterms FB2_18
	# !state_tras<2> & !state_tras<1> & state_tras<3> & 
	!state_tras<0> & key_entry2 & txd_buf<4> & !txd_buf<5> & 
	div8_tras_reg<0> & div8_tras_reg<1> & div8_tras_reg<2>
;Imported pterms FB2_3
	# !state_tras<2> & !state_tras<1> & state_tras<3> & 
	state_tras<0> & key_entry2 & !txd_buf<4> & div8_tras_reg<0> & 
	div8_tras_reg<1> & div8_tras_reg<2>
	# !state_tras<2> & !state_tras<1> & state_tras<3> & 
	key_entry2 & !txd_buf<4> & txd_buf<5> & div8_tras_reg<0> & 
	div8_tras_reg<1> & div8_tras_reg<2>;
   txd_buf<4>.CLK = clkbaud8x;
   txd_buf<4>.AR = !rst;

MACROCELL | 1 | 7 | txd_buf<5>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 8 | 1 | 1 | 1 | 7 | 1 | 0 | 1 | 2 | 1 | 6 | 1 | 8 | 1 | 9 | 1 | 17
INPUTS | 14 | key_entry2  | txd_buf<5>  | key_entry1  | state_tras<2>  | state_tras<3>  | div8_tras_reg<0>  | txd_buf<6>  | div8_tras_reg<1>  | div8_tras_reg<2>  | state_tras<0>  | state_tras<3>.EXP  | EXP11_.EXP  | clkbaud8x  | rst
INPUTMC | 13 | 1 | 10 | 1 | 7 | 0 | 1 | 1 | 11 | 1 | 6 | 1 | 4 | 1 | 17 | 1 | 13 | 1 | 12 | 1 | 15 | 1 | 6 | 1 | 8 | 7 | 14
INPUTP | 1 | 79
IMPORTS | 2 | 1 | 6 | 1 | 8
EQ | 43 | 
   txd_buf<5>.T = !key_entry2 & !txd_buf<5> & key_entry1
	# state_tras<2> & !state_tras<3> & key_entry2 & 
	txd_buf<5> & div8_tras_reg<0> & !txd_buf<6> & div8_tras_reg<1> & 
	div8_tras_reg<2>
	# !state_tras<3> & state_tras<0> & key_entry2 & 
	txd_buf<5> & div8_tras_reg<0> & !txd_buf<6> & div8_tras_reg<1> & 
	div8_tras_reg<2>
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