⭐ 欢迎来到虫虫下载站！ | 📦 资源下载 📁 资源专辑 ℹ️ 关于我们
⭐ 虫虫下载站
📤 上传资源

📄 uart.mfd

📁 Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档
💻 MFD
📖 第 1 页 / 共 5 页
字号:
🔍
12345 
	div8_rec_reg<2>
	# rxd_buf<4> & !rxd_buf<3> & !state_rec<0> & 
	!state_rec<1> & !state_rec<2> & state_rec<3> & div8_rec_reg<0> & 
	div8_rec_reg<1> & div8_rec_reg<2>
	# !rxd_buf<4> & rxd_buf<3> & !state_rec<0> & 
	!state_rec<1> & !state_rec<2> & state_rec<3> & div8_rec_reg<0> & 
	div8_rec_reg<1> & div8_rec_reg<2>;
   rxd_buf<3>.CLK = clkbaud8x;
   rxd_buf<3>.AR = !rst;

MACROCELL | 5 | 17 | rxd_buf<7>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 18 | 3 | 4 | 5 | 17 | 3 | 0 | 5 | 8 | 5 | 9 | 5 | 7 | 5 | 3 | 7 | 15 | 5 | 1 | 3 | 1 | 3 | 2 | 3 | 3 | 5 | 0 | 5 | 2 | 5 | 6 | 5 | 10 | 5 | 16 | 7 | 14
INPUTS | 13 | rxd_buf<7>  | state_rec<0>  | state_rec<3>  | div8_rec_reg<0>  | div8_rec_reg<1>  | div8_rec_reg<2>  | rxd_reg2  | state_rec<1>  | state_rec<2>  | clkbaud8x  | rst  | state_rec<2>.EXP  | en_6_OBUF$BUF1.EXP
INPUTMC | 12 | 5 | 17 | 5 | 15 | 5 | 4 | 2 | 13 | 5 | 13 | 5 | 12 | 7 | 0 | 5 | 2 | 5 | 0 | 7 | 14 | 5 | 0 | 5 | 16
INPUTP | 1 | 79
IMPORTS | 2 | 5 | 0 | 5 | 16
EQ | 22 | 
   rxd_buf<7>.T = rxd_buf<7> & state_rec<0> & !state_rec<3> & 
	div8_rec_reg<0> & div8_rec_reg<1> & div8_rec_reg<2> & !rxd_reg2
	# rxd_buf<7> & state_rec<1> & !state_rec<3> & 
	div8_rec_reg<0> & div8_rec_reg<1> & div8_rec_reg<2> & !rxd_reg2
	# rxd_buf<7> & state_rec<2> & !state_rec<3> & 
	div8_rec_reg<0> & div8_rec_reg<1> & div8_rec_reg<2> & !rxd_reg2
;Imported pterms FB6_1
	# !rxd_buf<7> & !state_rec<0> & !state_rec<1> & 
	!state_rec<2> & state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2> & rxd_reg2
;Imported pterms FB6_17
	# !rxd_buf<7> & state_rec<0> & !state_rec<3> & 
	div8_rec_reg<0> & div8_rec_reg<1> & div8_rec_reg<2> & rxd_reg2
	# !rxd_buf<7> & state_rec<1> & !state_rec<3> & 
	div8_rec_reg<0> & div8_rec_reg<1> & div8_rec_reg<2> & rxd_reg2
	# !rxd_buf<7> & state_rec<2> & !state_rec<3> & 
	div8_rec_reg<0> & div8_rec_reg<1> & div8_rec_reg<2> & rxd_reg2
	# rxd_buf<7> & !state_rec<0> & !state_rec<1> & 
	!state_rec<2> & state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2> & !rxd_reg2;
   rxd_buf<7>.CLK = clkbaud8x;
   rxd_buf<7>.AR = !rst;

MACROCELL | 1 | 3 | send_state<0>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 8 | 6 | 6 | 1 | 14 | 1 | 10 | 6 | 3 | 1 | 5 | 6 | 12 | 6 | 16 | 6 | 9
INPUTS | 10 | clkbaud8x  | rst  | state_tras<2>  | state_tras<1>  | state_tras<3>  | state_tras<0>  | key_entry2  | div8_tras_reg<0>  | div8_tras_reg<1>  | div8_tras_reg<2>
INPUTMC | 9 | 7 | 14 | 1 | 11 | 1 | 2 | 1 | 6 | 1 | 15 | 1 | 10 | 1 | 4 | 1 | 13 | 1 | 12
INPUTP | 1 | 79
EQ | 6 | 
   send_state<0>.T = Vcc;
   send_state<0>.CLK = clkbaud8x;
   send_state<0>.AR = !rst;
   send_state<0>.CE = state_tras<2> & state_tras<1> & state_tras<3> & 
	state_tras<0> & key_entry2 & div8_tras_reg<0> & div8_tras_reg<1> & 
	div8_tras_reg<2>;

MACROCELL | 6 | 14 | txd_buf<0>
ATTRIBUTES | 8520496 | 0
OUTPUTMC | 5 | 6 | 8 | 6 | 14 | 6 | 6 | 6 | 7 | 6 | 13
INPUTS | 11 | state_tras<1>  | state_tras<3>  | state_tras<0>  | key_entry2  | txd_buf<0>  | div8_tras_reg<0>  | div8_tras_reg<1>  | EXP28_.EXP  | EXP29_.EXP  | clkbaud8x  | rst
INPUTMC | 10 | 1 | 2 | 1 | 6 | 1 | 15 | 1 | 10 | 6 | 14 | 1 | 4 | 1 | 13 | 6 | 13 | 6 | 15 | 7 | 14
INPUTP | 1 | 79
IMPORTS | 2 | 6 | 13 | 6 | 15
EQ | 33 | 
   !txd_buf<0>.D = key_entry2 & !txd_buf<0> & !div8_tras_reg<0>
	# key_entry2 & !txd_buf<0> & !div8_tras_reg<1>
	# state_tras<1> & state_tras<3> & !state_tras<0> & 
	key_entry2 & !txd_buf<0>
;Imported pterms FB7_14
	# key_entry2 & !txd_buf<0> & !div8_tras_reg<2>
	# !key_entry2 & !txd_buf<0> & !key_entry1
	# state_tras<2> & !state_tras<1> & state_tras<3> & 
	key_entry2 & !txd_buf<0>
	# !state_tras<2> & state_tras<1> & state_tras<3> & 
	key_entry2 & !txd_buf<0>
	# !state_tras<2> & !state_tras<1> & !state_tras<3> & 
	!state_tras<0> & key_entry2 & !txd_buf<0>
;Imported pterms FB7_13
	# state_tras<2> & state_tras<1> & state_tras<3> & 
	state_tras<0> & key_entry2 & !send_state<1> & !send_state<2> & 
	send_state<0> & div8_tras_reg<0> & div8_tras_reg<1> & 
	div8_tras_reg<2>
;Imported pterms FB7_16
	# state_tras<2> & !state_tras<3> & key_entry2 & 
	div8_tras_reg<0> & !txd_buf<1> & div8_tras_reg<1> & div8_tras_reg<2>
	# state_tras<1> & !state_tras<3> & key_entry2 & 
	div8_tras_reg<0> & !txd_buf<1> & div8_tras_reg<1> & div8_tras_reg<2>
	# !state_tras<3> & state_tras<0> & key_entry2 & 
	div8_tras_reg<0> & !txd_buf<1> & div8_tras_reg<1> & div8_tras_reg<2>
	# !state_tras<2> & !state_tras<1> & state_tras<3> & 
	!state_tras<0> & key_entry2 & div8_tras_reg<0> & !txd_buf<1> & 
	div8_tras_reg<1> & div8_tras_reg<2>
	# state_tras<2> & state_tras<1> & state_tras<3> & 
	state_tras<0> & key_entry2 & send_state<1> & send_state<2> & 
	div8_tras_reg<0> & div8_tras_reg<1> & div8_tras_reg<2>;
   txd_buf<0>.CLK = clkbaud8x;
   txd_buf<0>.AR = !rst;

MACROCELL | 5 | 15 | state_rec<0>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 24 | 3 | 13 | 3 | 7 | 3 | 6 | 3 | 4 | 3 | 17 | 3 | 15 | 3 | 9 | 5 | 17 | 5 | 15 | 5 | 2 | 5 | 0 | 5 | 4 | 5 | 5 | 5 | 6 | 3 | 2 | 3 | 3 | 3 | 5 | 3 | 8 | 3 | 10 | 3 | 12 | 3 | 14 | 3 | 16 | 5 | 14 | 5 | 16
INPUTS | 11 | state_rec<0>  | state_rec<1>  | state_rec<2>  | state_rec<3>  | recstart_tmp  | div8_rec_reg<0>  | div8_rec_reg<1>  | div8_rec_reg<2>  | clkbaud8x  | rst  | en_6_OBUF$BUF2.EXP
INPUTMC | 10 | 5 | 15 | 5 | 2 | 5 | 0 | 5 | 4 | 5 | 5 | 2 | 13 | 5 | 13 | 5 | 12 | 7 | 14 | 5 | 14
INPUTP | 1 | 79
IMPORTS | 1 | 5 | 14
EQ | 13 | 
   state_rec<0>.T = !state_rec<0> & !state_rec<1> & !state_rec<2> & 
	!state_rec<3> & recstart_tmp
	# state_rec<2> & !state_rec<3> & div8_rec_reg<0> & 
	div8_rec_reg<1> & div8_rec_reg<2>
	# !state_rec<1> & !state_rec<2> & state_rec<3> & 
	div8_rec_reg<0> & div8_rec_reg<1> & div8_rec_reg<2>
;Imported pterms FB6_15
	# state_rec<0> & !state_rec<3> & div8_rec_reg<0> & 
	div8_rec_reg<1> & div8_rec_reg<2>
	# state_rec<1> & !state_rec<3> & div8_rec_reg<0> & 
	div8_rec_reg<1> & div8_rec_reg<2>;
   state_rec<0>.CLK = clkbaud8x;
   state_rec<0>.AR = !rst;

MACROCELL | 5 | 2 | state_rec<1>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 24 | 3 | 13 | 3 | 7 | 3 | 6 | 3 | 4 | 3 | 17 | 3 | 15 | 3 | 9 | 5 | 17 | 5 | 15 | 5 | 0 | 5 | 4 | 5 | 5 | 5 | 6 | 3 | 2 | 3 | 3 | 3 | 5 | 3 | 8 | 3 | 10 | 3 | 12 | 3 | 14 | 3 | 16 | 5 | 14 | 5 | 16 | 5 | 1
INPUTS | 15 | state_rec<0>  | state_rec<3>  | div8_rec_reg<0>  | div8_rec_reg<1>  | div8_rec_reg<2>  | clkbaud8x  | rst  | rxd_buf<4>  | rxd_buf<5>  | rxd_buf<6>  | rxd_buf<2>  | rxd_buf<0>  | rxd_buf<3>  | rxd_buf<7>  | rxd_buf<1>
INPUTMC | 14 | 5 | 15 | 5 | 4 | 2 | 13 | 5 | 13 | 5 | 12 | 7 | 14 | 3 | 7 | 3 | 6 | 3 | 4 | 3 | 17 | 3 | 15 | 3 | 9 | 5 | 17 | 3 | 13
INPUTP | 1 | 79
EXPORTS | 1 | 5 | 1
EQ | 9 | 
   state_rec<1>.T = state_rec<0> & !state_rec<3> & div8_rec_reg<0> & 
	div8_rec_reg<1> & div8_rec_reg<2>;
   state_rec<1>.CLK = clkbaud8x;
   state_rec<1>.AR = !rst;
    state_rec<1>.EXP  =  !rxd_buf<4> & !rxd_buf<5> & rxd_buf<6> & 
	rxd_buf<2> & !rxd_buf<0> & !rxd_buf<3> & !rxd_buf<7>
	# !rxd_buf<1> & !rxd_buf<4> & !rxd_buf<5> & 
	rxd_buf<6> & !rxd_buf<2> & rxd_buf<0> & !rxd_buf<3> & 
	!rxd_buf<7>

MACROCELL | 5 | 0 | state_rec<2>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 21 | 3 | 13 | 3 | 7 | 3 | 5 | 3 | 3 | 3 | 17 | 3 | 15 | 3 | 9 | 5 | 17 | 5 | 15 | 5 | 4 | 5 | 5 | 5 | 6 | 3 | 2 | 3 | 4 | 3 | 8 | 3 | 10 | 3 | 12 | 3 | 14 | 3 | 16 | 5 | 0 | 5 | 16
INPUTS | 11 | state_rec<0>  | state_rec<1>  | state_rec<3>  | div8_rec_reg<0>  | div8_rec_reg<1>  | div8_rec_reg<2>  | clkbaud8x  | rst  | rxd_buf<7>  | state_rec<2>  | rxd_reg2
INPUTMC | 10 | 5 | 15 | 5 | 2 | 5 | 4 | 2 | 13 | 5 | 13 | 5 | 12 | 7 | 14 | 5 | 17 | 5 | 0 | 7 | 0
INPUTP | 1 | 79
EXPORTS | 1 | 5 | 17
EQ | 7 | 
   state_rec<2>.T = state_rec<0> & state_rec<1> & !state_rec<3> & 
	div8_rec_reg<0> & div8_rec_reg<1> & div8_rec_reg<2>;
   state_rec<2>.CLK = clkbaud8x;
   state_rec<2>.AR = !rst;
    state_rec<2>.EXP  =  !rxd_buf<7> & !state_rec<0> & !state_rec<1> & 
	!state_rec<2> & state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2> & rxd_reg2

MACROCELL | 6 | 17 | trasstart
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 7 | 6 | 7 | 1 | 14 | 6 | 17 | 1 | 4 | 1 | 13 | 1 | 12 | 6 | 16
INPUTS | 11 | state_tras<2>  | state_tras<1>  | state_tras<3>  | state_tras<0>  | send_state<1>  | trasstart  | send_state<2>  | EXP30_.EXP  | clkbaud8x  | rst  | key_entry2
INPUTMC | 10 | 1 | 11 | 1 | 2 | 1 | 6 | 1 | 15 | 1 | 9 | 6 | 17 | 1 | 5 | 6 | 16 | 7 | 14 | 1 | 10
INPUTP | 1 | 79
IMPORTS | 1 | 6 | 16
EQ | 22 | 
   trasstart.T = !state_tras<2> & !state_tras<1> & !state_tras<3> & 
	!state_tras<0> & !send_state<1> & !trasstart
	# !state_tras<2> & !state_tras<1> & !state_tras<3> & 
	!state_tras<0> & !send_state<2> & !trasstart
;Imported pterms FB7_17
	# !state_tras<2> & !state_tras<1> & !state_tras<3> & 
	!state_tras<0> & !send_state<0> & !trasstart
	# state_tras<2> & !state_tras<1> & state_tras<3> & 
	!trasstart & div8_tras_reg<0> & div8_tras_reg<1> & 
	div8_tras_reg<2>
	# state_tras<2> & state_tras<3> & !state_tras<0> & 
	!trasstart & div8_tras_reg<0> & div8_tras_reg<1> & 
	div8_tras_reg<2>
	# !state_tras<2> & state_tras<1> & state_tras<3> & 
	!trasstart & div8_tras_reg<0> & div8_tras_reg<1> & 
	div8_tras_reg<2>
	# state_tras<2> & state_tras<1> & state_tras<3> & 
	state_tras<0> & trasstart & div8_tras_reg<0> & div8_tras_reg<1> & 
	div8_tras_reg<2>;
   trasstart.CLK = clkbaud8x;
   trasstart.AR = !rst;
   trasstart.CE = key_entry2;

MACROCELL | 0 | 11 | cnt_delay<0>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 22 | 0 | 0 | 0 | 11 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 12 | 0 | 10 | 0 | 9 | 0 | 8 | 0 | 7 | 0 | 6 | 0 | 13 | 2 | 17 | 2 | 16 | 2 | 15 | 2 | 14 | 0 | 5 | 0 | 4 | 0 | 3 | 0 | 2 | 0 | 1
INPUTS | 23 | cnt_delay<0>  | cnt_delay<10>  | cnt_delay<12>  | cnt_delay<13>  | cnt_delay<18>  | cnt_delay<8>  | cnt_delay<11>  | cnt_delay<14>  | cnt_delay<15>  | cnt_delay<16>  | cnt_delay<17>  | cnt_delay<19>  | cnt_delay<1>  | cnt_delay<2>  | cnt_delay<3>  | cnt_delay<4>  | cnt_delay<5>  | cnt_delay<6>  | cnt_delay<7>  | cnt_delay<9>  | clk  | rst  | start_delaycnt
INPUTMC | 21 | 0 | 11 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 12 | 0 | 10 | 0 | 9 | 0 | 8 | 0 | 7 | 0 | 6 | 0 | 13 | 2 | 17 | 2 | 16 | 2 | 15 | 2 | 14 | 0 | 5 | 0 | 4 | 0 | 3 | 0 | 2 | 0 | 0
INPUTP | 2 | 143 | 79
EQ | 9 | 
   !cnt_delay<0>.T = !cnt_delay<0> & cnt_delay<10> & cnt_delay<12> & 
	cnt_delay<13> & cnt_delay<18> & cnt_delay<8> & !cnt_delay<11> & 
	!cnt_delay<14> & !cnt_delay<15> & !cnt_delay<16> & !cnt_delay<17> & 
	cnt_delay<19> & !cnt_delay<1> & !cnt_delay<2> & !cnt_delay<3> & 
	!cnt_delay<4> & !cnt_delay<5> & !cnt_delay<6> & !cnt_delay<7> & 
	!cnt_delay<9>;
   cnt_delay<0>.CLK = clk;
   cnt_delay<0>.AR = !rst;
   cnt_delay<0>.CE = start_delaycnt;

MACROCELL | 0 | 17 | cnt_delay<10>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 14 | 0 | 0 | 0 | 11 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 12 | 0 | 10 | 0 | 9 | 0 | 8 | 0 | 7 | 0 | 6 | 0 | 13 | 0 | 1
INPUTS | 23 | cnt_delay<0>  | cnt_delay<8>  | cnt_delay<1>  | cnt_delay<2>  | cnt_delay<3>  | cnt_delay<4>  | cnt_delay<5>  | cnt_delay<6>  | cnt_delay<7>  | cnt_delay<9>  | cnt_delay<10>  | cnt_delay<12>  | cnt_delay<13>  | cnt_delay<18>  | cnt_delay<11>  | cnt_delay<14>  | cnt_delay<15>  | cnt_delay<16>  | cnt_delay<17>  | cnt_delay<19>  | clk  | rst  | start_delaycnt
INPUTMC | 21 | 0 | 11 | 0 | 12 | 2 | 17 | 2 | 16 | 2 | 15 | 2 | 14 | 0 | 5 | 0 | 4 | 0 | 3 | 0 | 2 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 10 | 0 | 9 | 0 | 8 | 0 | 7 | 0 | 6 | 0 | 13 | 0 | 0
INPUTP | 2 | 143 | 79
EQ | 12 | 
   cnt_delay<10>.T = cnt_delay<0> & cnt_delay<8> & cnt_delay<1> & 
	cnt_delay<2> & cnt_delay<3> & cnt_delay<4> & cnt_delay<5> & 
	cnt_delay<6> & cnt_delay<7> & cnt_delay<9>
	# !cnt_delay<0> & cnt_delay<10> & cnt_delay<12> & 
	cnt_delay<13> & cnt_delay<18> & cnt_delay<8> & !cnt_delay<11> & 
	!cnt_delay<14> & !cnt_delay<15> & !cnt_delay<16> & !cnt_delay<17> & 
	cnt_delay<19> & !cnt_delay<1> & !cnt_delay<2> & !cnt_delay<3> & 
	!cnt_delay<4> & !cnt_delay<5> & !cnt_delay<6> & !cnt_delay<7> & 
	!cnt_delay<9>;
   cnt_delay<10>.CLK = clk;
   cnt_delay<10>.AR = !rst;
   cnt_delay<10>.CE = start_delaycnt;

MACROCELL | 0 | 16 | cnt_delay<12>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 13 | 0 | 0 | 0 | 11 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 12 | 0 | 9 | 0 | 8 | 0 | 7 | 0 | 6 | 0 | 13 | 0 | 1
INPUTS | 23 | cnt_delay<0>  | cnt_delay<10>  | cnt_delay<8>  | cnt_delay<11>  | cnt_delay<1>  | cnt_delay<2>  | cnt_delay<3>  | cnt_delay<4>  | cnt_delay<5>  | cnt_delay<6>  | cnt_delay<7>  | cnt_delay<9>  | cnt_delay<12>  | cnt_delay<13>  | cnt_delay<18>  | cnt_delay<14>  | cnt_delay<15>  | cnt_delay<16>  | cnt_delay<17>  | cnt_delay<19>  | clk  | rst  | start_delaycnt
INPUTMC | 21 | 0 | 11 | 0 | 17 | 0 | 12 | 0 | 10 | 2 | 17 | 2 | 16 | 2 | 15 | 2 | 14 | 0 | 5 | 0 | 4 | 0 | 3 | 0 | 2 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 9 | 0 | 8 | 0 | 7 | 0 | 6 | 0 | 13 | 0 | 0
INPUTP | 2 | 143 | 79
EQ | 13 | 
   cnt_delay<12>.T = cnt_delay<0> & cnt_delay<10> & cnt_delay<8> & 
	cnt_delay<11> & cnt_delay<1> & cnt_delay<2> & cnt_delay<3> & 
	cnt_delay<4> & cnt_delay<5> & cnt_delay<6> & cnt_delay<7> & 
	cnt_delay<9>
	# !cnt_delay<0> & cnt_delay<10> & cnt_delay<12> & 
	cnt_delay<13> & cnt_delay<18> & cnt_delay<8> & !cnt_delay<11> & 
	!cnt_delay<14> & !cnt_delay<15> & !cnt_delay<16> & !cnt_delay<17> & 
	cnt_delay<19> & !cnt_delay<1> & !cnt_delay<2> & !cnt_delay<3> & 
	!cnt_delay<4> & !cnt_delay<5> & !cnt_delay<6> & !cnt_delay<7> & 
	!cnt_delay<9>;
   cnt_delay<12>.CLK = clk;
   cnt_delay<12>.AR = !rst;
   cnt_delay<12>.CE = start_delaycnt;
12345

⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -