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📁 Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档
💻 MFD
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MDF Database:  version 1.0
MDF_INFO | uart | XC95144XL-10-TQ144
MACROCELL | 6 | 9 | txd_reg
ATTRIBUTES | 8782818 | 0
OUTPUTMC | 4 | 6 | 8 | 6 | 6 | 6 | 7 | 6 | 10
INPUTS | 14 | state_tras<2>  | state_tras<1>  | state_tras<3>  | state_tras<0>  | send_state<1>  | send_state<2>  | div8_tras_reg<0>  | div8_tras_reg<1>  | div8_tras_reg<2>  | send_state<0>  | EXP25_.EXP  | clkbaud8x  | rst  | key_entry2
INPUTMC | 13 | 1 | 11 | 1 | 2 | 1 | 6 | 1 | 15 | 1 | 9 | 1 | 5 | 1 | 4 | 1 | 13 | 1 | 12 | 1 | 3 | 6 | 8 | 7 | 14 | 1 | 10
INPUTP | 1 | 79
EXPORTS | 1 | 6 | 10
IMPORTS | 1 | 6 | 8
EQ | 34 | 
   txd.D = ;Imported pterms FB7_9
	  txd & !div8_tras_reg<0>
	# txd & !div8_tras_reg<1>
	# txd & !div8_tras_reg<2>
	# txd & state_tras<2> & state_tras<3>
	# !state_tras<3> & state_tras<0> & txd_buf<0> & 
	div8_tras_reg<0> & div8_tras_reg<1> & div8_tras_reg<2>
;Imported pterms FB7_8
	# txd & state_tras<1> & state_tras<3>
	# txd & !state_tras<2> & !state_tras<1> & 
	!state_tras<3> & !state_tras<0> & !trasstart
	# state_tras<2> & !state_tras<3> & txd_buf<0> & 
	div8_tras_reg<0> & div8_tras_reg<1> & div8_tras_reg<2>
	# state_tras<1> & !state_tras<3> & txd_buf<0> & 
	div8_tras_reg<0> & div8_tras_reg<1> & div8_tras_reg<2>
	# !state_tras<2> & !state_tras<1> & state_tras<3> & 
	state_tras<0> & div8_tras_reg<0> & div8_tras_reg<1> & 
	div8_tras_reg<2>
;Imported pterms FB7_7
	# !state_tras<2> & !state_tras<1> & state_tras<3> & 
	txd_buf<0> & div8_tras_reg<0> & div8_tras_reg<1> & 
	div8_tras_reg<2>
	# txd & !state_tras<2> & !state_tras<1> & 
	!state_tras<3> & !state_tras<0> & send_state<1> & send_state<2> & 
	send_state<0>;
   txd.CLK = clkbaud8x;
   txd.AP = !rst;
   txd.CE = key_entry2;
    txd_reg.EXP  =  state_tras<2> & state_tras<1> & state_tras<3> & 
	state_tras<0> & key_entry2 & send_state<1> & send_state<2> & 
	div8_tras_reg<0> & div8_tras_reg<1> & div8_tras_reg<2>
	# state_tras<2> & state_tras<1> & state_tras<3> & 
	state_tras<0> & key_entry2 & send_state<1> & !send_state<0> & 
	div8_tras_reg<0> & div8_tras_reg<1> & div8_tras_reg<2>

MACROCELL | 7 | 14 | clkbaud8x
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 40 | 6 | 9 | 1 | 11 | 1 | 2 | 3 | 13 | 3 | 7 | 3 | 6 | 3 | 4 | 1 | 6 | 1 | 15 | 3 | 17 | 3 | 15 | 1 | 10 | 1 | 9 | 1 | 5 | 3 | 9 | 5 | 17 | 1 | 3 | 6 | 14 | 5 | 15 | 5 | 2 | 5 | 0 | 6 | 17 | 5 | 4 | 6 | 12 | 6 | 6 | 1 | 1 | 1 | 7 | 2 | 13 | 1 | 4 | 5 | 5 | 6 | 3 | 1 | 17 | 5 | 13 | 1 | 13 | 5 | 6 | 5 | 12 | 1 | 12 | 7 | 1 | 7 | 0 | 7 | 15
INPUTS | 26 | clk  | rst  | div_reg<0>  | div_reg<10>  | div_reg<11>  | div_reg<12>  | div_reg<13>  | div_reg<14>  | div_reg<1>  | div_reg<2>  | div_reg<3>  | div_reg<4>  | div_reg<5>  | div_reg<6>  | div_reg<7>  | div_reg<8>  | div_reg<9>  | div_reg<15>  | rxd_buf<1>  | rxd_buf<4>  | rxd_buf<5>  | rxd_buf<6>  | rxd_buf<2>  | rxd_buf<0>  | rxd_buf<3>  | rxd_buf<7>
INPUTMC | 24 | 2 | 11 | 7 | 13 | 7 | 12 | 7 | 11 | 7 | 10 | 7 | 9 | 2 | 12 | 7 | 17 | 7 | 7 | 7 | 6 | 7 | 5 | 7 | 4 | 7 | 3 | 7 | 16 | 7 | 2 | 7 | 8 | 3 | 13 | 3 | 7 | 3 | 6 | 3 | 4 | 3 | 17 | 3 | 15 | 3 | 9 | 5 | 17
INPUTP | 2 | 143 | 79
EXPORTS | 1 | 7 | 15
EQ | 11 | 
   clkbaud8x.T = Vcc;
   clkbaud8x.CLK = clk;
   clkbaud8x.AR = !rst;
   clkbaud8x.CE = div_reg<0> & !div_reg<10> & !div_reg<11> & 
	!div_reg<12> & !div_reg<13> & !div_reg<14> & div_reg<1> & 
	!div_reg<2> & !div_reg<3> & !div_reg<4> & !div_reg<5> & 
	!div_reg<6> & !div_reg<7> & div_reg<8> & !div_reg<9> & 
	!div_reg<15>;
    clkbaud8x.EXP  =  rxd_buf<1> & !rxd_buf<4> & !rxd_buf<5> & 
	rxd_buf<6> & !rxd_buf<2> & !rxd_buf<0> & !rxd_buf<3> & 
	!rxd_buf<7>

MACROCELL | 1 | 11 | state_tras<2>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 31 | 6 | 8 | 1 | 2 | 1 | 14 | 1 | 10 | 1 | 9 | 1 | 5 | 1 | 3 | 6 | 13 | 6 | 17 | 6 | 11 | 6 | 5 | 1 | 1 | 1 | 7 | 6 | 2 | 1 | 17 | 1 | 0 | 1 | 6 | 1 | 8 | 1 | 15 | 1 | 16 | 6 | 0 | 6 | 1 | 6 | 3 | 6 | 4 | 6 | 6 | 6 | 7 | 6 | 9 | 6 | 10 | 6 | 12 | 6 | 15 | 6 | 16
INPUTS | 8 | state_tras<1>  | state_tras<0>  | key_entry2  | div8_tras_reg<0>  | div8_tras_reg<1>  | div8_tras_reg<2>  | clkbaud8x  | rst
INPUTMC | 7 | 1 | 2 | 1 | 15 | 1 | 10 | 1 | 4 | 1 | 13 | 1 | 12 | 7 | 14
INPUTP | 1 | 79
EQ | 4 | 
   state_tras<2>.T = state_tras<1> & state_tras<0> & key_entry2 & 
	div8_tras_reg<0> & div8_tras_reg<1> & div8_tras_reg<2>;
   state_tras<2>.CLK = clkbaud8x;
   state_tras<2>.AR = !rst;

MACROCELL | 1 | 2 | state_tras<1>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 31 | 6 | 7 | 1 | 11 | 1 | 2 | 1 | 14 | 1 | 10 | 1 | 9 | 1 | 5 | 1 | 3 | 6 | 14 | 6 | 17 | 6 | 12 | 6 | 5 | 1 | 1 | 1 | 6 | 6 | 2 | 1 | 16 | 1 | 0 | 1 | 8 | 1 | 15 | 1 | 17 | 6 | 0 | 6 | 1 | 6 | 3 | 6 | 4 | 6 | 6 | 6 | 9 | 6 | 10 | 6 | 11 | 6 | 13 | 6 | 15 | 6 | 16
INPUTS | 12 | state_tras<0>  | key_entry2  | div8_tras_reg<0>  | div8_tras_reg<1>  | div8_tras_reg<2>  | clkbaud8x  | rst  | state_tras<2>  | state_tras<1>  | state_tras<3>  | txd_buf<4>  | txd_buf<5>
INPUTMC | 11 | 1 | 15 | 1 | 10 | 1 | 4 | 1 | 13 | 1 | 12 | 7 | 14 | 1 | 11 | 1 | 2 | 1 | 6 | 1 | 1 | 1 | 7
INPUTP | 1 | 79
EXPORTS | 1 | 1 | 1
EQ | 10 | 
   state_tras<1>.T = state_tras<0> & key_entry2 & div8_tras_reg<0> & 
	div8_tras_reg<1> & div8_tras_reg<2>;
   state_tras<1>.CLK = clkbaud8x;
   state_tras<1>.AR = !rst;
    state_tras<1>.EXP  =  !state_tras<2> & !state_tras<1> & state_tras<3> & 
	state_tras<0> & key_entry2 & !txd_buf<4> & div8_tras_reg<0> & 
	div8_tras_reg<1> & div8_tras_reg<2>
	# !state_tras<2> & !state_tras<1> & state_tras<3> & 
	key_entry2 & !txd_buf<4> & txd_buf<5> & div8_tras_reg<0> & 
	div8_tras_reg<1> & div8_tras_reg<2>

MACROCELL | 0 | 0 | start_delaycnt
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 21 | 0 | 0 | 0 | 11 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 12 | 0 | 10 | 0 | 9 | 0 | 8 | 0 | 7 | 0 | 6 | 0 | 13 | 2 | 17 | 2 | 16 | 2 | 15 | 2 | 14 | 0 | 5 | 0 | 4 | 0 | 3 | 0 | 2
INPUTS | 24 | start_delaycnt  | cnt_delay<0>  | cnt_delay<10>  | cnt_delay<12>  | cnt_delay<13>  | cnt_delay<18>  | cnt_delay<8>  | cnt_delay<11>  | cnt_delay<14>  | cnt_delay<15>  | cnt_delay<16>  | cnt_delay<17>  | cnt_delay<19>  | cnt_delay<1>  | cnt_delay<2>  | cnt_delay<3>  | cnt_delay<4>  | cnt_delay<5>  | cnt_delay<6>  | cnt_delay<7>  | cnt_delay<9>  | key_input  | clk  | rst
INPUTMC | 21 | 0 | 0 | 0 | 11 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 12 | 0 | 10 | 0 | 9 | 0 | 8 | 0 | 7 | 0 | 6 | 0 | 13 | 2 | 17 | 2 | 16 | 2 | 15 | 2 | 14 | 0 | 5 | 0 | 4 | 0 | 3 | 0 | 2
INPUTP | 3 | 78 | 143 | 79
EQ | 14 | 
   start_delaycnt.T = start_delaycnt & !cnt_delay<0> & cnt_delay<10> & 
	cnt_delay<12> & cnt_delay<13> & cnt_delay<18> & cnt_delay<8> & 
	!cnt_delay<11> & !cnt_delay<14> & !cnt_delay<15> & !cnt_delay<16> & 
	!cnt_delay<17> & cnt_delay<19> & !cnt_delay<1> & !cnt_delay<2> & 
	!cnt_delay<3> & !cnt_delay<4> & !cnt_delay<5> & !cnt_delay<6> & 
	!cnt_delay<7> & !cnt_delay<9>
	# !key_input & !start_delaycnt & !cnt_delay<0> & 
	!cnt_delay<10> & !cnt_delay<12> & !cnt_delay<13> & !cnt_delay<18> & 
	!cnt_delay<8> & !cnt_delay<11> & !cnt_delay<14> & !cnt_delay<15> & 
	!cnt_delay<16> & !cnt_delay<17> & !cnt_delay<19> & !cnt_delay<1> & 
	!cnt_delay<2> & !cnt_delay<3> & !cnt_delay<4> & !cnt_delay<5> & 
	!cnt_delay<6> & !cnt_delay<7> & !cnt_delay<9>;
   start_delaycnt.CLK = clk;
   start_delaycnt.AR = !rst;

MACROCELL | 3 | 13 | rxd_buf<1>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 16 | 3 | 13 | 3 | 15 | 3 | 0 | 5 | 8 | 5 | 9 | 5 | 7 | 5 | 3 | 7 | 15 | 5 | 1 | 3 | 1 | 3 | 12 | 3 | 14 | 5 | 2 | 5 | 6 | 5 | 10 | 7 | 14
INPUTS | 12 | rxd_buf<1>  | rxd_buf<2>  | state_rec<0>  | state_rec<3>  | div8_rec_reg<0>  | div8_rec_reg<1>  | div8_rec_reg<2>  | state_rec<1>  | state_rec<2>  | clkbaud8x  | rst  | EXP16_.EXP
INPUTMC | 11 | 3 | 13 | 3 | 17 | 5 | 15 | 5 | 4 | 2 | 13 | 5 | 13 | 5 | 12 | 5 | 2 | 5 | 0 | 7 | 14 | 3 | 12
INPUTP | 1 | 79
IMPORTS | 1 | 3 | 12
EQ | 27 | 
   rxd_buf<1>.T = rxd_buf<1> & !rxd_buf<2> & state_rec<0> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
	# rxd_buf<1> & !rxd_buf<2> & state_rec<1> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
	# rxd_buf<1> & !rxd_buf<2> & state_rec<2> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
;Imported pterms FB4_13
	# !rxd_buf<1> & rxd_buf<2> & state_rec<0> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
	# !rxd_buf<1> & rxd_buf<2> & state_rec<1> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
	# !rxd_buf<1> & rxd_buf<2> & state_rec<2> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
	# rxd_buf<1> & !rxd_buf<2> & !state_rec<0> & 
	!state_rec<1> & !state_rec<2> & state_rec<3> & div8_rec_reg<0> & 
	div8_rec_reg<1> & div8_rec_reg<2>
	# !rxd_buf<1> & rxd_buf<2> & !state_rec<0> & 
	!state_rec<1> & !state_rec<2> & state_rec<3> & div8_rec_reg<0> & 
	div8_rec_reg<1> & div8_rec_reg<2>;
   rxd_buf<1>.CLK = clkbaud8x;
   rxd_buf<1>.AR = !rst;

MACROCELL | 3 | 7 | rxd_buf<4>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 17 | 3 | 7 | 3 | 9 | 3 | 0 | 5 | 8 | 5 | 9 | 5 | 7 | 5 | 3 | 7 | 15 | 5 | 1 | 3 | 1 | 3 | 6 | 3 | 8 | 3 | 10 | 5 | 2 | 5 | 6 | 5 | 10 | 7 | 14
INPUTS | 13 | rxd_buf<4>  | rxd_buf<5>  | state_rec<0>  | state_rec<3>  | div8_rec_reg<0>  | div8_rec_reg<1>  | div8_rec_reg<2>  | state_rec<1>  | state_rec<2>  | clkbaud8x  | rst  | rxd_buf<5>.EXP  | en_6_OBUF$BUF5.EXP
INPUTMC | 12 | 3 | 7 | 3 | 6 | 5 | 15 | 5 | 4 | 2 | 13 | 5 | 13 | 5 | 12 | 5 | 2 | 5 | 0 | 7 | 14 | 3 | 6 | 3 | 8
INPUTP | 1 | 79
IMPORTS | 2 | 3 | 6 | 3 | 8
EQ | 28 | 
   rxd_buf<4>.T = rxd_buf<4> & !rxd_buf<5> & state_rec<0> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
	# rxd_buf<4> & !rxd_buf<5> & state_rec<1> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
	# rxd_buf<4> & !rxd_buf<5> & state_rec<2> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
;Imported pterms FB4_7
	# !rxd_buf<4> & rxd_buf<5> & state_rec<0> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
;Imported pterms FB4_9
	# !rxd_buf<4> & rxd_buf<5> & state_rec<1> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
	# !rxd_buf<4> & rxd_buf<5> & state_rec<2> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
	# rxd_buf<4> & !rxd_buf<5> & !state_rec<0> & 
	!state_rec<1> & !state_rec<2> & state_rec<3> & div8_rec_reg<0> & 
	div8_rec_reg<1> & div8_rec_reg<2>
	# !rxd_buf<4> & rxd_buf<5> & !state_rec<0> & 
	!state_rec<1> & !state_rec<2> & state_rec<3> & div8_rec_reg<0> & 
	div8_rec_reg<1> & div8_rec_reg<2>;
   rxd_buf<4>.CLK = clkbaud8x;
   rxd_buf<4>.AR = !rst;

MACROCELL | 3 | 6 | rxd_buf<5>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 17 | 3 | 7 | 3 | 6 | 3 | 0 | 5 | 8 | 5 | 9 | 5 | 7 | 5 | 3 | 7 | 15 | 5 | 1 | 3 | 1 | 3 | 4 | 3 | 5 | 3 | 8 | 5 | 2 | 5 | 6 | 5 | 10 | 7 | 14
INPUTS | 12 | rxd_buf<5>  | rxd_buf<6>  | state_rec<0>  | state_rec<3>  | div8_rec_reg<0>  | div8_rec_reg<1>  | div8_rec_reg<2>  | state_rec<1>  | rxd_buf<4>  | clkbaud8x  | rst  | EXP15_.EXP
INPUTMC | 11 | 3 | 6 | 3 | 4 | 5 | 15 | 5 | 4 | 2 | 13 | 5 | 13 | 5 | 12 | 5 | 2 | 3 | 7 | 7 | 14 | 3 | 5
INPUTP | 1 | 79
EXPORTS | 1 | 3 | 7
IMPORTS | 1 | 3 | 5
EQ | 31 | 
   rxd_buf<5>.T = rxd_buf<5> & !rxd_buf<6> & state_rec<0> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
	# rxd_buf<5> & !rxd_buf<6> & state_rec<1> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
;Imported pterms FB4_6
	# rxd_buf<5> & !rxd_buf<6> & state_rec<2> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
	# !rxd_buf<5> & rxd_buf<6> & state_rec<0> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
	# !rxd_buf<5> & rxd_buf<6> & state_rec<1> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
	# !rxd_buf<5> & rxd_buf<6> & state_rec<2> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
	# rxd_buf<5> & !rxd_buf<6> & !state_rec<0> & 
	!state_rec<1> & !state_rec<2> & state_rec<3> & div8_rec_reg<0> & 
	div8_rec_reg<1> & div8_rec_reg<2>
;Imported pterms FB4_5
	# !rxd_buf<5> & rxd_buf<6> & !state_rec<0> & 
	!state_rec<1> & !state_rec<2> & state_rec<3> & div8_rec_reg<0> & 
	div8_rec_reg<1> & div8_rec_reg<2>;
   rxd_buf<5>.CLK = clkbaud8x;
   rxd_buf<5>.AR = !rst;
    rxd_buf<5>.EXP  =  !rxd_buf<4> & rxd_buf<5> & state_rec<0> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>

MACROCELL | 3 | 4 | rxd_buf<6>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 17 | 3 | 6 | 3 | 4 | 3 | 0 | 5 | 8 | 5 | 9 | 5 | 7 | 5 | 3 | 7 | 15 | 5 | 1 | 3 | 1 | 3 | 2 | 3 | 3 | 3 | 5 | 5 | 2 | 5 | 6 | 5 | 10 | 7 | 14
INPUTS | 13 | rxd_buf<6>  | rxd_buf<7>  | state_rec<0>  | state_rec<3>  | div8_rec_reg<0>  | div8_rec_reg<1>  | div8_rec_reg<2>  | state_rec<1>  | rxd_buf<5>  | clkbaud8x  | rst  | state_rec<2>  | EXP14_.EXP
INPUTMC | 12 | 3 | 4 | 5 | 17 | 5 | 15 | 5 | 4 | 2 | 13 | 5 | 13 | 5 | 12 | 5 | 2 | 3 | 6 | 7 | 14 | 5 | 0 | 3 | 3
INPUTP | 1 | 79
EXPORTS | 1 | 3 | 5
IMPORTS | 1 | 3 | 3
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