📄 uart.vm6

📁 Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档
💻 VM6
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OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
SIGNAL | NODE | start_delaycnt.CLKF | 11510 | ? | 0 | 4096 | start_delaycnt | NULL | NULL | start_delaycnt.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | clk_IBUF
OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF
SIGNAL | NODE | start_delaycnt.RSTF | 11511 | ? | 0 | 4096 | start_delaycnt | NULL | NULL | start_delaycnt.SI | 6 | 9 | MC_SI_RSTF
SPPTERM | 1 | IV_FALSE | rst_IBUF

SRFF_INSTANCE | start_delaycnt.REG | start_delaycnt | 0 | 3 | 1
INPUT_NODE_TYPE | 0 | 8 | SRFF_D
NODE | start_delaycnt.D | 11507 | ? | 0 | 0 | start_delaycnt | NULL | NULL | start_delaycnt.XOR | 0 | 7 | ALU_F
INPUT_NODE_TYPE | 1 | 8 | SRFF_C
SIGNAL | NODE | start_delaycnt.CLKF | 11510 | ? | 0 | 4096 | start_delaycnt | NULL | NULL | start_delaycnt.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | clk_IBUF
INPUT_NODE_TYPE | 3 | 8 | SRFF_R
SIGNAL | NODE | start_delaycnt.RSTF | 11511 | ? | 0 | 4096 | start_delaycnt | NULL | NULL | start_delaycnt.SI | 6 | 9 | MC_SI_RSTF
SPPTERM | 1 | IV_FALSE | rst_IBUF
OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
NODE | start_delaycnt.Q | 11512 | ? | 0 | 0 | start_delaycnt | NULL | NULL | start_delaycnt.REG | 0 | 8 | SRFF_Q

MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | rxd_buf<1> | uart_COPY_0_COPY_0 | 2155877376 | 12 | 1
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rxd_buf<1> | 11370 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | rxd_buf<1>.Q | rxd_buf<1> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rxd_buf<2> | 11376 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | rxd_buf<2>.Q | rxd_buf<2> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | state_rec<0> | 11385 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | state_rec<0>.Q | state_rec<0> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | state_rec<3> | 11395 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | state_rec<3>.Q | state_rec<3> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div8_rec_reg<0> | 11414 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div8_rec_reg<0>.Q | div8_rec_reg<0> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div8_rec_reg<1> | 11419 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div8_rec_reg<1>.Q | div8_rec_reg<1> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div8_rec_reg<2> | 11422 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div8_rec_reg<2>.Q | div8_rec_reg<2> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | state_rec<1> | 11386 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | state_rec<1>.Q | state_rec<1> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | state_rec<2> | 11387 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | state_rec<2>.Q | state_rec<2> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clkbaud8x | 11366 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | clkbaud8x.Q | clkbaud8x | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rst_IBUF | 11362 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | NULL | rst_IBUF | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | EXP16_.EXP | 12088 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | EXP16_.EXP | EXP16_ | 4 | 0 | MC_EXPORT
OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
NODE | rxd_buf<1> | 11370 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | rxd_buf<1>.Q | rxd_buf<1> | 1 | 0 | MC_UIM

SIGNAL_INSTANCE | rxd_buf<1>.SI | rxd_buf<1> | 0 | 12 | 4
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rxd_buf<1> | 11370 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | rxd_buf<1>.Q | rxd_buf<1> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rxd_buf<2> | 11376 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | rxd_buf<2>.Q | rxd_buf<2> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | state_rec<0> | 11385 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | state_rec<0>.Q | state_rec<0> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | state_rec<3> | 11395 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | state_rec<3>.Q | state_rec<3> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div8_rec_reg<0> | 11414 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div8_rec_reg<0>.Q | div8_rec_reg<0> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div8_rec_reg<1> | 11419 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div8_rec_reg<1>.Q | div8_rec_reg<1> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div8_rec_reg<2> | 11422 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div8_rec_reg<2>.Q | div8_rec_reg<2> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | state_rec<1> | 11386 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | state_rec<1>.Q | state_rec<1> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | state_rec<2> | 11387 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | state_rec<2>.Q | state_rec<2> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clkbaud8x | 11366 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | clkbaud8x.Q | clkbaud8x | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rst_IBUF | 11362 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | NULL | rst_IBUF | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | EXP16_.EXP | 12088 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | EXP16_.EXP | EXP16_ | 4 | 0 | MC_EXPORT
OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
SIGNAL | NODE | rxd_buf<1>.D1 | 11514 | ? | 0 | 4096 | rxd_buf<1> | NULL | NULL | rxd_buf<1>.SI | 1 | 9 | MC_SI_D1
SPPTERM | 0 | IV_ZERO
OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
SIGNAL | NODE | rxd_buf<1>.D2 | 11515 | ? | 0 | 4096 | rxd_buf<1> | NULL | NULL | rxd_buf<1>.SI | 2 | 9 | MC_SI_D2
SPPTERM | 1 | IV_TRUE | EXP16_.EXP
SPPTERM | 7 | IV_TRUE | rxd_buf<1> | IV_FALSE | rxd_buf<2> | IV_TRUE | state_rec<0> | IV_FALSE | state_rec<3> | IV_TRUE | div8_rec_reg<0> | IV_TRUE | div8_rec_reg<1> | IV_TRUE | div8_rec_reg<2>
SPPTERM | 7 | IV_TRUE | rxd_buf<1> | IV_FALSE | rxd_buf<2> | IV_TRUE | state_rec<1> | IV_FALSE | state_rec<3> | IV_TRUE | div8_rec_reg<0> | IV_TRUE | div8_rec_reg<1> | IV_TRUE | div8_rec_reg<2>
SPPTERM | 7 | IV_TRUE | rxd_buf<1> | IV_FALSE | rxd_buf<2> | IV_TRUE | state_rec<2> | IV_FALSE | state_rec<3> | IV_TRUE | div8_rec_reg<0> | IV_TRUE | div8_rec_reg<1> | IV_TRUE | div8_rec_reg<2>
OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
SIGNAL | NODE | rxd_buf<1>.CLKF | 11516 | ? | 0 | 4096 | rxd_buf<1> | NULL | NULL | rxd_buf<1>.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | clkbaud8x
OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF
SIGNAL | NODE | rxd_buf<1>.RSTF | 11517 | ? | 0 | 4096 | rxd_buf<1> | NULL | NULL | rxd_buf<1>.SI | 6 | 9 | MC_SI_RSTF
SPPTERM | 1 | IV_FALSE | rst_IBUF

SRFF_INSTANCE | rxd_buf<1>.REG | rxd_buf<1> | 0 | 3 | 1
INPUT_NODE_TYPE | 0 | 8 | SRFF_D
NODE | rxd_buf<1>.D | 11513 | ? | 0 | 0 | rxd_buf<1> | NULL | NULL | rxd_buf<1>.XOR | 0 | 7 | ALU_F
INPUT_NODE_TYPE | 1 | 8 | SRFF_C
SIGNAL | NODE | rxd_buf<1>.CLKF | 11516 | ? | 0 | 4096 | rxd_buf<1> | NULL | NULL | rxd_buf<1>.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | clkbaud8x
INPUT_NODE_TYPE | 3 | 8 | SRFF_R
SIGNAL | NODE | rxd_buf<1>.RSTF | 11517 | ? | 0 | 4096 | rxd_buf<1> | NULL | NULL | rxd_buf<1>.SI | 6 | 9 | MC_SI_RSTF
SPPTERM | 1 | IV_FALSE | rst_IBUF
OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
NODE | rxd_buf<1>.Q | 11518 | ? | 0 | 0 | rxd_buf<1> | NULL | NULL | rxd_buf<1>.REG | 0 | 8 | SRFF_Q

MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | rxd_buf<4> | uart_COPY_0_COPY_0 | 2155877376 | 13 | 1
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rxd_buf<4> | 11371 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | rxd_buf<4>.Q | rxd_buf<4> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rxd_buf<5> | 11372 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | rxd_buf<5>.Q | rxd_buf<5> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | state_rec<0> | 11385 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | state_rec<0>.Q | state_rec<0> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | state_rec<3> | 11395 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | state_rec<3>.Q | state_rec<3> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div8_rec_reg<0> | 11414 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div8_rec_reg<0>.Q | div8_rec_reg<0> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div8_rec_reg<1> | 11419 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div8_rec_reg<1>.Q | div8_rec_reg<1> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div8_rec_reg<2> | 11422 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div8_rec_reg<2>.Q | div8_rec_reg<2> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | state_rec<1> | 11386 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | state_rec<1>.Q | state_rec<1> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | state_rec<2> | 11387 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | state_rec<2>.Q | state_rec<2> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clkbaud8x | 11366 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | clkbaud8x.Q | clkbaud8x | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rst_IBUF | 11362 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | NULL | rst_IBUF | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rxd_buf<5>.EXP | 12084 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | rxd_buf<5>.EXP | rxd_buf<5> | 4 | 0 | MC_EXPORT
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | en_6_OBUF$BUF5.EXP | 12085 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | en_6_OBUF$BUF5.EXP | en_6_OBUF$BUF5 | 4 | 0 | MC_EXPORT
OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
NODE | rxd_buf<4> | 11371 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | rxd_buf<4>.Q | rxd_buf<4> | 1 | 0 | MC_UIM

SIGNAL_INSTANCE | rxd_buf<4>.SI | rxd_buf<4> | 0 | 13 | 4
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rxd_buf<4> | 11371 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | rxd_buf<4>.Q | rxd_buf<4> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rxd_buf<5> | 11372 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | rxd_buf<5>.Q | rxd_buf<5> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | state_rec<0> | 11385 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | state_rec<0>.Q | state_rec<0> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | state_rec<3> | 11395 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | state_rec<3>.Q | state_rec<3> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div8_rec_reg<0> | 11414 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div8_rec_reg<0>.Q | div8_rec_reg<0> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div8_rec_reg<1> | 11419 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div8_rec_reg<1>.Q | div8_rec_reg<1> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div8_rec_reg<2> | 11422 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div8_rec_reg<2>.Q | div8_rec_reg<2> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | state_rec<1> | 11386 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | state_rec<1>.Q | state_rec<1> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | state_rec<2> | 11387 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | state_rec<2>.Q | state_rec<2> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clkbaud8x | 11366 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | clkbaud8x.Q | clkbaud8x | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rst_IBUF | 11362 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | NULL | rst_IBUF | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rxd_buf<5>.EXP | 12084 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | rxd_buf<5>.EXP | rxd_buf<5> | 4 | 0 | MC_EXPORT
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | en_6_OBUF$BUF5.EXP | 12085 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | en_6_OBUF$BUF5.EXP | en_6_OBUF$BUF5 | 4 | 0 | MC_EXPORT
OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
SIGNAL | NODE | rxd_buf<4>.D1 | 11520 | ? | 0 | 4096 | rxd_buf<4> | NULL | NULL | rxd_buf<4>.SI | 1 | 9 | MC_SI_D1
SPPTERM | 0 | IV_ZERO
OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
SIGNAL | NODE | rxd_buf<4>.D2 | 11521 | ? | 0 | 4096 | rxd_buf<4> | NULL | NULL | rxd_buf<4>.SI | 2 | 9 | MC_SI_D2
SPPTERM | 1 | IV_TRUE | rxd_buf<5>.EXP
SPPTERM | 1 | IV_TRUE | en_6_OBUF$BUF5.EXP
SPPTERM | 7 | IV_TRUE | rxd_buf<4> | IV_FALSE | rxd_buf<5> | IV_TRUE | state_rec<0> | IV_FALSE | state_rec<3> | IV_TRUE | div8_rec_reg<0> | IV_TRUE | div8_rec_reg<1> | IV_TRUE | div8_rec_reg<2>
SPPTERM | 7 | IV_TRUE | rxd_buf<4> | IV_FALSE | rxd_buf<5> | IV_TRUE | state_rec<1> | IV_FALSE | state_rec<3> | IV_TRUE | div8_rec_reg<0> | IV_TRUE | div8_rec_reg<1> | IV_TRUE | div8_rec_reg<2>
SPPTERM | 7 | IV_TRUE | rxd_buf<4> | IV_FALSE | rxd_buf<5> | IV_TRUE | state_rec<2> | IV_FALSE | state_rec<3> | IV_TRUE | div8_rec_reg<0> | IV_TRUE | div8_rec_reg<1> | IV_TRUE | div8_rec_reg<2>
OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
SIGNAL | NODE | rxd_buf<4>.CLKF | 11522 | ? | 0 | 4096 | rxd_buf<4> | NULL | NULL | rxd_buf<4>.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | clkbaud8x
OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF
SIGNAL | NODE | rxd_buf<4>.RSTF | 11523 | ? | 0 | 4096 | rxd_buf<4> | NULL | NULL | rxd_buf<4>.SI | 6 | 9 | MC_SI_RSTF
SPPTERM | 1 | IV_FALSE | rst_IBUF

SRFF_INSTANCE | rxd_buf<4>.REG | rxd_buf<4> | 0 | 3 | 1
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