uart.vm6

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | state_tras<1> | 11368 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | state_tras<1>.Q | state_tras<1> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | state_tras<3> | 11374 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | state_tras<3>.Q | state_tras<3> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | txd_buf<4> | 11398 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | txd_buf<4>.Q | txd_buf<4> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | txd_buf<5> | 11399 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | txd_buf<5>.Q | txd_buf<5> | 1 | 0 | MC_UIM
OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
NODE | state_tras<1> | 11368 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | state_tras<1>.Q | state_tras<1> | 1 | 0 | MC_UIM
OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT
NODE | state_tras<1>.EXP | 12057 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | state_tras<1>.EXP | state_tras<1> | 4 | 0 | MC_EXPORT

SIGNAL_INSTANCE | state_tras<1>.SI | state_tras<1> | 0 | 12 | 5
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | state_tras<0> | 11375 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | state_tras<0>.Q | state_tras<0> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | key_entry2 | 11378 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | key_entry2.Q | key_entry2 | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div8_tras_reg<0> | 11415 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div8_tras_reg<0>.Q | div8_tras_reg<0> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div8_tras_reg<1> | 11420 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div8_tras_reg<1>.Q | div8_tras_reg<1> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div8_tras_reg<2> | 11423 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div8_tras_reg<2>.Q | div8_tras_reg<2> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clkbaud8x | 11366 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | clkbaud8x.Q | clkbaud8x | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rst_IBUF | 11362 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | NULL | rst_IBUF | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | state_tras<2> | 11367 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | state_tras<2>.Q | state_tras<2> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | state_tras<1> | 11368 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | state_tras<1>.Q | state_tras<1> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | state_tras<3> | 11374 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | state_tras<3>.Q | state_tras<3> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | txd_buf<4> | 11398 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | txd_buf<4>.Q | txd_buf<4> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | txd_buf<5> | 11399 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | txd_buf<5>.Q | txd_buf<5> | 1 | 0 | MC_UIM
OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
SIGNAL | NODE | state_tras<1>.D1 | 11502 | ? | 0 | 4096 | state_tras<1> | NULL | NULL | state_tras<1>.SI | 1 | 9 | MC_SI_D1
SPPTERM | 0 | IV_ZERO
OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
SIGNAL | NODE | state_tras<1>.D2 | 11503 | ? | 0 | 4096 | state_tras<1> | NULL | NULL | state_tras<1>.SI | 2 | 9 | MC_SI_D2
SPPTERM | 5 | IV_TRUE | state_tras<0> | IV_TRUE | key_entry2 | IV_TRUE | div8_tras_reg<0> | IV_TRUE | div8_tras_reg<1> | IV_TRUE | div8_tras_reg<2>
OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
SIGNAL | NODE | state_tras<1>.CLKF | 11504 | ? | 0 | 4096 | state_tras<1> | NULL | NULL | state_tras<1>.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | clkbaud8x
OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF
SIGNAL | NODE | state_tras<1>.RSTF | 11505 | ? | 0 | 4096 | state_tras<1> | NULL | NULL | state_tras<1>.SI | 6 | 9 | MC_SI_RSTF
SPPTERM | 1 | IV_FALSE | rst_IBUF
OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT
SIGNAL | NODE | state_tras<1>.EXP | 12046 | ? | 0 | 0 | state_tras<1> | NULL | NULL | state_tras<1>.SI | 7 | 9 | MC_SI_EXPORT
SPPTERM | 9 | IV_FALSE | state_tras<2> | IV_FALSE | state_tras<1> | IV_TRUE | state_tras<3> | IV_TRUE | state_tras<0> | IV_TRUE | key_entry2 | IV_FALSE | txd_buf<4> | IV_TRUE | div8_tras_reg<0> | IV_TRUE | div8_tras_reg<1> | IV_TRUE | div8_tras_reg<2>
SPPTERM | 9 | IV_FALSE | state_tras<2> | IV_FALSE | state_tras<1> | IV_TRUE | state_tras<3> | IV_TRUE | key_entry2 | IV_FALSE | txd_buf<4> | IV_TRUE | txd_buf<5> | IV_TRUE | div8_tras_reg<0> | IV_TRUE | div8_tras_reg<1> | IV_TRUE | div8_tras_reg<2>

SRFF_INSTANCE | state_tras<1>.REG | state_tras<1> | 0 | 3 | 1
INPUT_NODE_TYPE | 0 | 8 | SRFF_D
NODE | state_tras<1>.D | 11501 | ? | 0 | 0 | state_tras<1> | NULL | NULL | state_tras<1>.XOR | 0 | 7 | ALU_F
INPUT_NODE_TYPE | 1 | 8 | SRFF_C
SIGNAL | NODE | state_tras<1>.CLKF | 11504 | ? | 0 | 4096 | state_tras<1> | NULL | NULL | state_tras<1>.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | clkbaud8x
INPUT_NODE_TYPE | 3 | 8 | SRFF_R
SIGNAL | NODE | state_tras<1>.RSTF | 11505 | ? | 0 | 4096 | state_tras<1> | NULL | NULL | state_tras<1>.SI | 6 | 9 | MC_SI_RSTF
SPPTERM | 1 | IV_FALSE | rst_IBUF
OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
NODE | state_tras<1>.Q | 11506 | ? | 0 | 0 | state_tras<1> | NULL | NULL | state_tras<1>.REG | 0 | 8 | SRFF_Q

MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | start_delaycnt | uart_COPY_0_COPY_0 | 2155877376 | 24 | 1
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | start_delaycnt | 11369 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | start_delaycnt.Q | start_delaycnt | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cnt_delay<0> | 11389 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | cnt_delay<0>.Q | cnt_delay<0> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cnt_delay<10> | 11390 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | cnt_delay<10>.Q | cnt_delay<10> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cnt_delay<12> | 11391 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | cnt_delay<12>.Q | cnt_delay<12> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cnt_delay<13> | 11392 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | cnt_delay<13>.Q | cnt_delay<13> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cnt_delay<18> | 11393 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | cnt_delay<18>.Q | cnt_delay<18> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cnt_delay<8> | 11394 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | cnt_delay<8>.Q | cnt_delay<8> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cnt_delay<11> | 11400 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | cnt_delay<11>.Q | cnt_delay<11> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cnt_delay<14> | 11401 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | cnt_delay<14>.Q | cnt_delay<14> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cnt_delay<15> | 11402 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | cnt_delay<15>.Q | cnt_delay<15> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cnt_delay<16> | 11403 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | cnt_delay<16>.Q | cnt_delay<16> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cnt_delay<17> | 11404 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | cnt_delay<17>.Q | cnt_delay<17> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cnt_delay<19> | 11405 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | cnt_delay<19>.Q | cnt_delay<19> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cnt_delay<1> | 11406 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | cnt_delay<1>.Q | cnt_delay<1> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cnt_delay<2> | 11407 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | cnt_delay<2>.Q | cnt_delay<2> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cnt_delay<3> | 11408 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | cnt_delay<3>.Q | cnt_delay<3> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cnt_delay<4> | 11409 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | cnt_delay<4>.Q | cnt_delay<4> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cnt_delay<5> | 11410 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | cnt_delay<5>.Q | cnt_delay<5> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cnt_delay<6> | 11411 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | cnt_delay<6>.Q | cnt_delay<6> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cnt_delay<7> | 11412 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | cnt_delay<7>.Q | cnt_delay<7> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cnt_delay<9> | 11413 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | cnt_delay<9>.Q | cnt_delay<9> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | key_input_IBUF | 11361 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | NULL | key_input_IBUF | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clk_IBUF | 11365 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | NULL | clk_IBUF | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rst_IBUF | 11362 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | NULL | rst_IBUF | 0 | 5 | II_IMUX
OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
NODE | start_delaycnt | 11369 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | start_delaycnt.Q | start_delaycnt | 1 | 0 | MC_UIM

SIGNAL_INSTANCE | start_delaycnt.SI | start_delaycnt | 0 | 24 | 4
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | start_delaycnt | 11369 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | start_delaycnt.Q | start_delaycnt | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cnt_delay<0> | 11389 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | cnt_delay<0>.Q | cnt_delay<0> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cnt_delay<10> | 11390 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | cnt_delay<10>.Q | cnt_delay<10> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cnt_delay<12> | 11391 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | cnt_delay<12>.Q | cnt_delay<12> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cnt_delay<13> | 11392 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | cnt_delay<13>.Q | cnt_delay<13> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cnt_delay<18> | 11393 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | cnt_delay<18>.Q | cnt_delay<18> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cnt_delay<8> | 11394 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | cnt_delay<8>.Q | cnt_delay<8> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cnt_delay<11> | 11400 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | cnt_delay<11>.Q | cnt_delay<11> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cnt_delay<14> | 11401 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | cnt_delay<14>.Q | cnt_delay<14> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cnt_delay<15> | 11402 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | cnt_delay<15>.Q | cnt_delay<15> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cnt_delay<16> | 11403 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | cnt_delay<16>.Q | cnt_delay<16> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cnt_delay<17> | 11404 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | cnt_delay<17>.Q | cnt_delay<17> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cnt_delay<19> | 11405 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | cnt_delay<19>.Q | cnt_delay<19> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cnt_delay<1> | 11406 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | cnt_delay<1>.Q | cnt_delay<1> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cnt_delay<2> | 11407 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | cnt_delay<2>.Q | cnt_delay<2> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cnt_delay<3> | 11408 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | cnt_delay<3>.Q | cnt_delay<3> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cnt_delay<4> | 11409 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | cnt_delay<4>.Q | cnt_delay<4> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cnt_delay<5> | 11410 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | cnt_delay<5>.Q | cnt_delay<5> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cnt_delay<6> | 11411 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | cnt_delay<6>.Q | cnt_delay<6> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cnt_delay<7> | 11412 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | cnt_delay<7>.Q | cnt_delay<7> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cnt_delay<9> | 11413 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | cnt_delay<9>.Q | cnt_delay<9> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | key_input_IBUF | 11361 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | NULL | key_input_IBUF | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clk_IBUF | 11365 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | NULL | clk_IBUF | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rst_IBUF | 11362 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | NULL | rst_IBUF | 0 | 5 | II_IMUX
OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
SIGNAL | NODE | start_delaycnt.D1 | 11508 | ? | 0 | 0 | start_delaycnt | NULL | NULL | start_delaycnt.SI | 1 | 9 | MC_SI_D1
SPPTERM | 0 | IV_ZERO
OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
SIGNAL | NODE | start_delaycnt.D2 | 11509 | ? | 0 | 4096 | start_delaycnt | NULL | NULL | start_delaycnt.SI | 2 | 9 | MC_SI_D2
SPPTERM | 21 | IV_TRUE | start_delaycnt | IV_FALSE | cnt_delay<0> | IV_TRUE | cnt_delay<10> | IV_TRUE | cnt_delay<12> | IV_TRUE | cnt_delay<13> | IV_TRUE | cnt_delay<18> | IV_TRUE | cnt_delay<8> | IV_FALSE | cnt_delay<11> | IV_FALSE | cnt_delay<14> | IV_FALSE | cnt_delay<15> | IV_FALSE | cnt_delay<16> | IV_FALSE | cnt_delay<17> | IV_TRUE | cnt_delay<19> | IV_FALSE | cnt_delay<1> | IV_FALSE | cnt_delay<2> | IV_FALSE | cnt_delay<3> | IV_FALSE | cnt_delay<4> | IV_FALSE | cnt_delay<5> | IV_FALSE | cnt_delay<6> | IV_FALSE | cnt_delay<7> | IV_FALSE | cnt_delay<9>
SPPTERM | 22 | IV_FALSE | key_input_IBUF | IV_FALSE | start_delaycnt | IV_FALSE | cnt_delay<0> | IV_FALSE | cnt_delay<10> | IV_FALSE | cnt_delay<12> | IV_FALSE | cnt_delay<13> | IV_FALSE | cnt_delay<18> | IV_FALSE | cnt_delay<8> | IV_FALSE | cnt_delay<11> | IV_FALSE | cnt_delay<14> | IV_FALSE | cnt_delay<15> | IV_FALSE | cnt_delay<16> | IV_FALSE | cnt_delay<17> | IV_FALSE | cnt_delay<19> | IV_FALSE | cnt_delay<1> | IV_FALSE | cnt_delay<2> | IV_FALSE | cnt_delay<3> | IV_FALSE | cnt_delay<4> | IV_FALSE | cnt_delay<5> | IV_FALSE | cnt_delay<6> | IV_FALSE | cnt_delay<7> | IV_FALSE | cnt_delay<9>