uart.vm6

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rxd_buf<3> | 11381 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | rxd_buf<3>.Q | rxd_buf<3> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rxd_buf<7> | 11382 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | rxd_buf<7>.Q | rxd_buf<7> | 1 | 0 | MC_UIM
OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
NODE | clkbaud8x | 11366 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | clkbaud8x.Q | clkbaud8x | 1 | 0 | MC_UIM
OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT
NODE | clkbaud8x.EXP | 12140 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | clkbaud8x.EXP | clkbaud8x | 4 | 0 | MC_EXPORT

SIGNAL_INSTANCE | clkbaud8x.SI | clkbaud8x | 0 | 26 | 6
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clk_IBUF | 11365 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | NULL | clk_IBUF | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rst_IBUF | 11362 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | NULL | rst_IBUF | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div_reg<0> | 11425 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div_reg<0>.Q | div_reg<0> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div_reg<10> | 11426 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div_reg<10>.Q | div_reg<10> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div_reg<11> | 11427 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div_reg<11>.Q | div_reg<11> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div_reg<12> | 11428 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div_reg<12>.Q | div_reg<12> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div_reg<13> | 11429 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div_reg<13>.Q | div_reg<13> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div_reg<14> | 11430 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div_reg<14>.Q | div_reg<14> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div_reg<1> | 11431 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div_reg<1>.Q | div_reg<1> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div_reg<2> | 11432 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div_reg<2>.Q | div_reg<2> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div_reg<3> | 11433 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div_reg<3>.Q | div_reg<3> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div_reg<4> | 11434 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div_reg<4>.Q | div_reg<4> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div_reg<5> | 11435 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div_reg<5>.Q | div_reg<5> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div_reg<6> | 11436 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div_reg<6>.Q | div_reg<6> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div_reg<7> | 11437 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div_reg<7>.Q | div_reg<7> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div_reg<8> | 11438 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div_reg<8>.Q | div_reg<8> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div_reg<9> | 11439 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div_reg<9>.Q | div_reg<9> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div_reg<15> | 11440 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div_reg<15>.Q | div_reg<15> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rxd_buf<1> | 11370 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | rxd_buf<1>.Q | rxd_buf<1> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rxd_buf<4> | 11371 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | rxd_buf<4>.Q | rxd_buf<4> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rxd_buf<5> | 11372 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | rxd_buf<5>.Q | rxd_buf<5> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rxd_buf<6> | 11373 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | rxd_buf<6>.Q | rxd_buf<6> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rxd_buf<2> | 11376 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | rxd_buf<2>.Q | rxd_buf<2> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rxd_buf<0> | 11377 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | rxd_buf<0>.Q | rxd_buf<0> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rxd_buf<3> | 11381 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | rxd_buf<3>.Q | rxd_buf<3> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rxd_buf<7> | 11382 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | rxd_buf<7>.Q | rxd_buf<7> | 1 | 0 | MC_UIM
OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
SIGNAL | NODE | clkbaud8x.D1 | 11489 | ? | 0 | 4096 | clkbaud8x | NULL | NULL | clkbaud8x.SI | 1 | 9 | MC_SI_D1
SPPTERM | 0 | IV_ZERO
OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
SIGNAL | NODE | clkbaud8x.D2 | 11490 | ? | 0 | 4096 | clkbaud8x | NULL | NULL | clkbaud8x.SI | 2 | 9 | MC_SI_D2
SPPTERM | 0 | IV_DC
OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
SIGNAL | NODE | clkbaud8x.CLKF | 11491 | ? | 0 | 4096 | clkbaud8x | NULL | NULL | clkbaud8x.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | clk_IBUF
OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF
SIGNAL | NODE | clkbaud8x.RSTF | 11492 | ? | 0 | 4096 | clkbaud8x | NULL | NULL | clkbaud8x.SI | 6 | 9 | MC_SI_RSTF
SPPTERM | 1 | IV_FALSE | rst_IBUF
OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT
SIGNAL | NODE | clkbaud8x.EXP | 12139 | ? | 0 | 0 | clkbaud8x | NULL | NULL | clkbaud8x.SI | 7 | 9 | MC_SI_EXPORT
SPPTERM | 8 | IV_TRUE | rxd_buf<1> | IV_FALSE | rxd_buf<4> | IV_FALSE | rxd_buf<5> | IV_TRUE | rxd_buf<6> | IV_FALSE | rxd_buf<2> | IV_FALSE | rxd_buf<0> | IV_FALSE | rxd_buf<3> | IV_FALSE | rxd_buf<7>
OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE
SIGNAL | NODE | clkbaud8x.CE | 11493 | ? | 0 | 4096 | clkbaud8x | NULL | NULL | clkbaud8x.SI | 10 | 9 | MC_SI_CE
SPPTERM | 16 | IV_TRUE | div_reg<0> | IV_FALSE | div_reg<10> | IV_FALSE | div_reg<11> | IV_FALSE | div_reg<12> | IV_FALSE | div_reg<13> | IV_FALSE | div_reg<14> | IV_TRUE | div_reg<1> | IV_FALSE | div_reg<2> | IV_FALSE | div_reg<3> | IV_FALSE | div_reg<4> | IV_FALSE | div_reg<5> | IV_FALSE | div_reg<6> | IV_FALSE | div_reg<7> | IV_TRUE | div_reg<8> | IV_FALSE | div_reg<9> | IV_FALSE | div_reg<15>

SRFF_INSTANCE | clkbaud8x.REG | clkbaud8x | 0 | 4 | 1
INPUT_NODE_TYPE | 0 | 8 | SRFF_D
NODE | clkbaud8x.D | 11488 | ? | 0 | 0 | clkbaud8x | NULL | NULL | clkbaud8x.XOR | 0 | 7 | ALU_F
INPUT_NODE_TYPE | 1 | 8 | SRFF_C
SIGNAL | NODE | clkbaud8x.CLKF | 11491 | ? | 0 | 4096 | clkbaud8x | NULL | NULL | clkbaud8x.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | clk_IBUF
INPUT_NODE_TYPE | 3 | 8 | SRFF_R
SIGNAL | NODE | clkbaud8x.RSTF | 11492 | ? | 0 | 4096 | clkbaud8x | NULL | NULL | clkbaud8x.SI | 6 | 9 | MC_SI_RSTF
SPPTERM | 1 | IV_FALSE | rst_IBUF
INPUT_NODE_TYPE | 4 | 8 | SRFF_CE
SIGNAL | NODE | clkbaud8x.CE | 11493 | ? | 0 | 4096 | clkbaud8x | NULL | NULL | clkbaud8x.SI | 10 | 9 | MC_SI_CE
SPPTERM | 16 | IV_TRUE | div_reg<0> | IV_FALSE | div_reg<10> | IV_FALSE | div_reg<11> | IV_FALSE | div_reg<12> | IV_FALSE | div_reg<13> | IV_FALSE | div_reg<14> | IV_TRUE | div_reg<1> | IV_FALSE | div_reg<2> | IV_FALSE | div_reg<3> | IV_FALSE | div_reg<4> | IV_FALSE | div_reg<5> | IV_FALSE | div_reg<6> | IV_FALSE | div_reg<7> | IV_TRUE | div_reg<8> | IV_FALSE | div_reg<9> | IV_FALSE | div_reg<15>
OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
NODE | clkbaud8x.Q | 11494 | ? | 0 | 0 | clkbaud8x | NULL | NULL | clkbaud8x.REG | 0 | 8 | SRFF_Q

MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | state_tras<2> | uart_COPY_0_COPY_0 | 2155877376 | 8 | 1
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | state_tras<1> | 11368 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | state_tras<1>.Q | state_tras<1> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | state_tras<0> | 11375 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | state_tras<0>.Q | state_tras<0> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | key_entry2 | 11378 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | key_entry2.Q | key_entry2 | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div8_tras_reg<0> | 11415 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div8_tras_reg<0>.Q | div8_tras_reg<0> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div8_tras_reg<1> | 11420 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div8_tras_reg<1>.Q | div8_tras_reg<1> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div8_tras_reg<2> | 11423 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div8_tras_reg<2>.Q | div8_tras_reg<2> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clkbaud8x | 11366 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | clkbaud8x.Q | clkbaud8x | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rst_IBUF | 11362 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | NULL | rst_IBUF | 0 | 5 | II_IMUX
OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
NODE | state_tras<2> | 11367 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | state_tras<2>.Q | state_tras<2> | 1 | 0 | MC_UIM

SIGNAL_INSTANCE | state_tras<2>.SI | state_tras<2> | 0 | 8 | 4
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | state_tras<1> | 11368 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | state_tras<1>.Q | state_tras<1> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | state_tras<0> | 11375 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | state_tras<0>.Q | state_tras<0> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | key_entry2 | 11378 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | key_entry2.Q | key_entry2 | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div8_tras_reg<0> | 11415 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div8_tras_reg<0>.Q | div8_tras_reg<0> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div8_tras_reg<1> | 11420 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div8_tras_reg<1>.Q | div8_tras_reg<1> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div8_tras_reg<2> | 11423 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div8_tras_reg<2>.Q | div8_tras_reg<2> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clkbaud8x | 11366 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | clkbaud8x.Q | clkbaud8x | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rst_IBUF | 11362 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | NULL | rst_IBUF | 0 | 5 | II_IMUX
OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
SIGNAL | NODE | state_tras<2>.D1 | 11496 | ? | 0 | 4096 | state_tras<2> | NULL | NULL | state_tras<2>.SI | 1 | 9 | MC_SI_D1
SPPTERM | 0 | IV_ZERO
OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
SIGNAL | NODE | state_tras<2>.D2 | 11497 | ? | 0 | 4096 | state_tras<2> | NULL | NULL | state_tras<2>.SI | 2 | 9 | MC_SI_D2
SPPTERM | 6 | IV_TRUE | state_tras<1> | IV_TRUE | state_tras<0> | IV_TRUE | key_entry2 | IV_TRUE | div8_tras_reg<0> | IV_TRUE | div8_tras_reg<1> | IV_TRUE | div8_tras_reg<2>
OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
SIGNAL | NODE | state_tras<2>.CLKF | 11498 | ? | 0 | 4096 | state_tras<2> | NULL | NULL | state_tras<2>.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | clkbaud8x
OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF
SIGNAL | NODE | state_tras<2>.RSTF | 11499 | ? | 0 | 4096 | state_tras<2> | NULL | NULL | state_tras<2>.SI | 6 | 9 | MC_SI_RSTF
SPPTERM | 1 | IV_FALSE | rst_IBUF

SRFF_INSTANCE | state_tras<2>.REG | state_tras<2> | 0 | 3 | 1
INPUT_NODE_TYPE | 0 | 8 | SRFF_D
NODE | state_tras<2>.D | 11495 | ? | 0 | 0 | state_tras<2> | NULL | NULL | state_tras<2>.XOR | 0 | 7 | ALU_F
INPUT_NODE_TYPE | 1 | 8 | SRFF_C
SIGNAL | NODE | state_tras<2>.CLKF | 11498 | ? | 0 | 4096 | state_tras<2> | NULL | NULL | state_tras<2>.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | clkbaud8x
INPUT_NODE_TYPE | 3 | 8 | SRFF_R
SIGNAL | NODE | state_tras<2>.RSTF | 11499 | ? | 0 | 4096 | state_tras<2> | NULL | NULL | state_tras<2>.SI | 6 | 9 | MC_SI_RSTF
SPPTERM | 1 | IV_FALSE | rst_IBUF
OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
NODE | state_tras<2>.Q | 11500 | ? | 0 | 0 | state_tras<2> | NULL | NULL | state_tras<2>.REG | 0 | 8 | SRFF_Q

MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | state_tras<1> | uart_COPY_0_COPY_0 | 2155877376 | 12 | 2
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | state_tras<0> | 11375 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | state_tras<0>.Q | state_tras<0> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | key_entry2 | 11378 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | key_entry2.Q | key_entry2 | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div8_tras_reg<0> | 11415 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div8_tras_reg<0>.Q | div8_tras_reg<0> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div8_tras_reg<1> | 11420 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div8_tras_reg<1>.Q | div8_tras_reg<1> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div8_tras_reg<2> | 11423 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div8_tras_reg<2>.Q | div8_tras_reg<2> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clkbaud8x | 11366 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | clkbaud8x.Q | clkbaud8x | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rst_IBUF | 11362 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | NULL | rst_IBUF | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | state_tras<2> | 11367 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | state_tras<2>.Q | state_tras<2> | 1 | 0 | MC_UIM