uart.vm6

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

NDS Database:  version H.42

NDS_INFO | xc9500xl | 95144XL144TQ | XC95144XL-10-TQ144

DEVICE | 95144XL | 95144XL144TQ | 

NETWORK | uart | 0 | 0 | 16391

INPUT_INSTANCE | 0 | 0 | NULL | key_input_IBUF | uart_COPY_0_COPY_0 | 16 | 1 | 1
INPUT_NODE_TYPE | 0 | 5 | II_IN
NODE | key_input | 11477 | PI | 0 | 0 | uart_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
NODE | key_input_IBUF | 11361 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | NULL | key_input_IBUF | 0 | 5 | II_IMUX

INPUT_INSTANCE | 0 | 0 | NULL | rst_IBUF | uart_COPY_0_COPY_0 | 16 | 1 | 1
INPUT_NODE_TYPE | 0 | 5 | II_IN
NODE | rst | 11478 | PI | 0 | 0 | uart_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
NODE | rst_IBUF | 11362 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | NULL | rst_IBUF | 0 | 5 | II_IMUX

MACROCELL_INSTANCE | PrldLow+OptxMapped | txd_reg | uart_COPY_0_COPY_0 | 2155873280 | 14 | 3
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | state_tras<2> | 11367 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | state_tras<2>.Q | state_tras<2> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | state_tras<1> | 11368 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | state_tras<1>.Q | state_tras<1> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | state_tras<3> | 11374 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | state_tras<3>.Q | state_tras<3> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | state_tras<0> | 11375 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | state_tras<0>.Q | state_tras<0> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | send_state<1> | 11379 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | send_state<1>.Q | send_state<1> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | send_state<2> | 11380 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | send_state<2>.Q | send_state<2> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div8_tras_reg<0> | 11415 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div8_tras_reg<0>.Q | div8_tras_reg<0> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div8_tras_reg<1> | 11420 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div8_tras_reg<1>.Q | div8_tras_reg<1> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div8_tras_reg<2> | 11423 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div8_tras_reg<2>.Q | div8_tras_reg<2> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | send_state<0> | 11383 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | send_state<0>.Q | send_state<0> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | EXP25_.EXP | 12131 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | EXP25_.EXP | EXP25_ | 4 | 0 | MC_EXPORT
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clkbaud8x | 11366 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | clkbaud8x.Q | clkbaud8x | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rst_IBUF | 11362 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | NULL | rst_IBUF | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | key_entry2 | 11378 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | key_entry2.Q | key_entry2 | 1 | 0 | MC_UIM
OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
NODE | txd_reg$Q | 11363 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | txd_reg.Q | txd_reg | 0 | 0 | MC_Q
OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
NODE | txd_reg | 11364 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | txd_reg.Q | txd_reg | 1 | 0 | MC_UIM
OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT
NODE | txd_reg.EXP | 12132 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | txd_reg.EXP | txd_reg | 4 | 0 | MC_EXPORT

SIGNAL_INSTANCE | txd_reg.SI | txd_reg | 0 | 14 | 6
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | state_tras<2> | 11367 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | state_tras<2>.Q | state_tras<2> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | state_tras<1> | 11368 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | state_tras<1>.Q | state_tras<1> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | state_tras<3> | 11374 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | state_tras<3>.Q | state_tras<3> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | state_tras<0> | 11375 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | state_tras<0>.Q | state_tras<0> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | send_state<1> | 11379 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | send_state<1>.Q | send_state<1> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | send_state<2> | 11380 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | send_state<2>.Q | send_state<2> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div8_tras_reg<0> | 11415 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div8_tras_reg<0>.Q | div8_tras_reg<0> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div8_tras_reg<1> | 11420 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div8_tras_reg<1>.Q | div8_tras_reg<1> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div8_tras_reg<2> | 11423 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div8_tras_reg<2>.Q | div8_tras_reg<2> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | send_state<0> | 11383 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | send_state<0>.Q | send_state<0> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | EXP25_.EXP | 12131 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | EXP25_.EXP | EXP25_ | 4 | 0 | MC_EXPORT
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clkbaud8x | 11366 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | clkbaud8x.Q | clkbaud8x | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rst_IBUF | 11362 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | NULL | rst_IBUF | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | key_entry2 | 11378 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | key_entry2.Q | key_entry2 | 1 | 0 | MC_UIM
OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
SIGNAL | NODE | txd_reg.D1 | 11482 | ? | 0 | 4096 | txd_reg | NULL | NULL | txd_reg.SI | 1 | 9 | MC_SI_D1
SPPTERM | 0 | IV_ZERO
OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
SIGNAL | NODE | txd_reg.D2 | 11483 | ? | 0 | 4096 | txd_reg | NULL | NULL | txd_reg.SI | 2 | 9 | MC_SI_D2
SPPTERM | 1 | IV_TRUE | EXP25_.EXP
OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
SIGNAL | NODE | txd_reg.CLKF | 11484 | ? | 0 | 4096 | txd_reg | NULL | NULL | txd_reg.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | clkbaud8x
OUTPUT_NODE_TYPE | 5 | 9 | MC_SI_SETF
SIGNAL | NODE | txd_reg.SETF | 11485 | ? | 0 | 4096 | txd_reg | NULL | NULL | txd_reg.SI | 5 | 9 | MC_SI_SETF
SPPTERM | 1 | IV_FALSE | rst_IBUF
OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT
SIGNAL | NODE | txd_reg.EXP | 12116 | ? | 0 | 0 | txd_reg | NULL | NULL | txd_reg.SI | 7 | 9 | MC_SI_EXPORT
SPPTERM | 10 | IV_TRUE | state_tras<2> | IV_TRUE | state_tras<1> | IV_TRUE | state_tras<3> | IV_TRUE | state_tras<0> | IV_TRUE | key_entry2 | IV_TRUE | send_state<1> | IV_TRUE | send_state<2> | IV_TRUE | div8_tras_reg<0> | IV_TRUE | div8_tras_reg<1> | IV_TRUE | div8_tras_reg<2>
SPPTERM | 10 | IV_TRUE | state_tras<2> | IV_TRUE | state_tras<1> | IV_TRUE | state_tras<3> | IV_TRUE | state_tras<0> | IV_TRUE | key_entry2 | IV_TRUE | send_state<1> | IV_FALSE | send_state<0> | IV_TRUE | div8_tras_reg<0> | IV_TRUE | div8_tras_reg<1> | IV_TRUE | div8_tras_reg<2>
OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE
SIGNAL | NODE | txd_reg.CE | 11486 | ? | 0 | 4096 | txd_reg | NULL | NULL | txd_reg.SI | 10 | 9 | MC_SI_CE
SPPTERM | 1 | IV_TRUE | key_entry2

SRFF_INSTANCE | txd_reg.REG | txd_reg | 0 | 4 | 1
INPUT_NODE_TYPE | 0 | 8 | SRFF_D
NODE | txd_reg.D | 11481 | ? | 0 | 0 | txd_reg | NULL | NULL | txd_reg.XOR | 0 | 7 | ALU_F
INPUT_NODE_TYPE | 1 | 8 | SRFF_C
SIGNAL | NODE | txd_reg.CLKF | 11484 | ? | 0 | 4096 | txd_reg | NULL | NULL | txd_reg.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | clkbaud8x
INPUT_NODE_TYPE | 2 | 8 | SRFF_S
SIGNAL | NODE | txd_reg.SETF | 11485 | ? | 0 | 4096 | txd_reg | NULL | NULL | txd_reg.SI | 5 | 9 | MC_SI_SETF
SPPTERM | 1 | IV_FALSE | rst_IBUF
INPUT_NODE_TYPE | 4 | 8 | SRFF_CE
SIGNAL | NODE | txd_reg.CE | 11486 | ? | 0 | 4096 | txd_reg | NULL | NULL | txd_reg.SI | 10 | 9 | MC_SI_CE
SPPTERM | 1 | IV_TRUE | key_entry2
OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
NODE | txd_reg.Q | 11487 | ? | 0 | 0 | txd_reg | NULL | NULL | txd_reg.REG | 0 | 8 | SRFF_Q

INPUT_INSTANCE | 0 | 0 | NULL | clk_IBUF | uart_COPY_0_COPY_0 | 16 | 1 | 1
INPUT_NODE_TYPE | 0 | 5 | II_IN
NODE | clk | 11479 | PI | 0 | 0 | uart_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
NODE | clk_IBUF | 11365 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | NULL | clk_IBUF | 0 | 5 | II_IMUX

MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | clkbaud8x | uart_COPY_0_COPY_0 | 2155877376 | 26 | 2
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clk_IBUF | 11365 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | NULL | clk_IBUF | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rst_IBUF | 11362 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | NULL | rst_IBUF | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div_reg<0> | 11425 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div_reg<0>.Q | div_reg<0> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div_reg<10> | 11426 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div_reg<10>.Q | div_reg<10> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div_reg<11> | 11427 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div_reg<11>.Q | div_reg<11> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div_reg<12> | 11428 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div_reg<12>.Q | div_reg<12> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div_reg<13> | 11429 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div_reg<13>.Q | div_reg<13> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div_reg<14> | 11430 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div_reg<14>.Q | div_reg<14> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div_reg<1> | 11431 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div_reg<1>.Q | div_reg<1> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div_reg<2> | 11432 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div_reg<2>.Q | div_reg<2> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div_reg<3> | 11433 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div_reg<3>.Q | div_reg<3> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div_reg<4> | 11434 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div_reg<4>.Q | div_reg<4> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div_reg<5> | 11435 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div_reg<5>.Q | div_reg<5> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div_reg<6> | 11436 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div_reg<6>.Q | div_reg<6> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div_reg<7> | 11437 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div_reg<7>.Q | div_reg<7> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div_reg<8> | 11438 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div_reg<8>.Q | div_reg<8> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div_reg<9> | 11439 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div_reg<9>.Q | div_reg<9> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | div_reg<15> | 11440 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | div_reg<15>.Q | div_reg<15> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rxd_buf<1> | 11370 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | rxd_buf<1>.Q | rxd_buf<1> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rxd_buf<4> | 11371 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | rxd_buf<4>.Q | rxd_buf<4> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rxd_buf<5> | 11372 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | rxd_buf<5>.Q | rxd_buf<5> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rxd_buf<6> | 11373 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | rxd_buf<6>.Q | rxd_buf<6> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rxd_buf<2> | 11376 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | rxd_buf<2>.Q | rxd_buf<2> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rxd_buf<0> | 11377 | ? | 0 | 0 | uart_COPY_0_COPY_0 | NULL | rxd_buf<0>.Q | rxd_buf<0> | 1 | 0 | MC_UIM