uart.rpt

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

	OR (rxd_buf(7) AND state_rec(2) AND NOT state_rec(3) AND 
	div8_rec_reg(0) AND div8_rec_reg(1) AND div8_rec_reg(2) AND NOT rxd_reg2));

FDCPE_rxd_reg1: FDCPE port map (rxd_reg1,rxd,clkbaud8x,NOT rst,'0');

FDCPE_rxd_reg2: FDCPE port map (rxd_reg2,rxd_reg1,clkbaud8x,NOT rst,'0');


seg_data(0) <= '1';


seg_data(1) <= NOT (((en_6_OBUF$BUF4.EXP)
	OR (rxd_buf(1) AND NOT rxd_buf(4) AND NOT rxd_buf(5) AND 
	rxd_buf(6) AND NOT rxd_buf(3) AND NOT rxd_buf(7))
	OR (NOT rxd_buf(4) AND NOT rxd_buf(5) AND rxd_buf(6) AND 
	rxd_buf(0) AND NOT rxd_buf(3) AND NOT rxd_buf(7))
	OR (rxd_buf(1) AND rxd_buf(4) AND rxd_buf(5) AND 
	NOT rxd_buf(6) AND NOT rxd_buf(2) AND NOT rxd_buf(3) AND NOT rxd_buf(7))
	OR (rxd_buf(1) AND rxd_buf(4) AND rxd_buf(5) AND 
	NOT rxd_buf(6) AND NOT rxd_buf(0) AND NOT rxd_buf(3) AND NOT rxd_buf(7))
	OR (NOT rxd_buf(1) AND rxd_buf(4) AND rxd_buf(5) AND 
	NOT rxd_buf(6) AND rxd_buf(2) AND NOT rxd_buf(3) AND NOT rxd_buf(7))));


seg_data(2) <= NOT (((seg_data_3_OBUF.EXP)
	OR (rxd_buf(1) AND NOT rxd_buf(4) AND NOT rxd_buf(5) AND 
	rxd_buf(6) AND NOT rxd_buf(3) AND NOT rxd_buf(7))
	OR (NOT rxd_buf(1) AND rxd_buf(4) AND rxd_buf(5) AND 
	NOT rxd_buf(6) AND rxd_buf(2) AND NOT rxd_buf(3) AND NOT rxd_buf(7))
	OR (NOT rxd_buf(1) AND rxd_buf(4) AND rxd_buf(5) AND 
	NOT rxd_buf(6) AND NOT rxd_buf(2) AND NOT rxd_buf(0) AND NOT rxd_buf(7))
	OR (NOT rxd_buf(4) AND NOT rxd_buf(5) AND rxd_buf(6) AND 
	NOT rxd_buf(2) AND rxd_buf(0) AND NOT rxd_buf(3) AND NOT rxd_buf(7))));


seg_data(3) <= NOT (((en_6_OBUF.EXP)
	OR (rxd_buf(1) AND NOT rxd_buf(4) AND NOT rxd_buf(5) AND 
	rxd_buf(6) AND NOT rxd_buf(3) AND NOT rxd_buf(7))
	OR (NOT rxd_buf(4) AND NOT rxd_buf(5) AND rxd_buf(6) AND 
	rxd_buf(2) AND NOT rxd_buf(3) AND NOT rxd_buf(7))
	OR (NOT rxd_buf(1) AND rxd_buf(4) AND rxd_buf(5) AND 
	NOT rxd_buf(6) AND NOT rxd_buf(2) AND NOT rxd_buf(0) AND NOT rxd_buf(7))));


seg_data(4) <= NOT (((recstart.EXP)
	OR (seg_data_2_OBUF.EXP)
	OR (rxd_buf(1) AND rxd_buf(4) AND rxd_buf(5) AND 
	NOT rxd_buf(6) AND NOT rxd_buf(2) AND NOT rxd_buf(3) AND NOT rxd_buf(7))
	OR (rxd_buf(1) AND rxd_buf(4) AND rxd_buf(5) AND 
	NOT rxd_buf(6) AND NOT rxd_buf(0) AND NOT rxd_buf(3) AND NOT rxd_buf(7))
	OR (NOT rxd_buf(1) AND rxd_buf(4) AND rxd_buf(5) AND 
	NOT rxd_buf(6) AND NOT rxd_buf(2) AND NOT rxd_buf(0) AND NOT rxd_buf(7))
	OR (NOT rxd_buf(1) AND NOT rxd_buf(4) AND NOT rxd_buf(5) AND 
	rxd_buf(6) AND rxd_buf(2) AND NOT rxd_buf(3) AND NOT rxd_buf(7))
	OR (NOT rxd_buf(4) AND NOT rxd_buf(5) AND rxd_buf(6) AND 
	rxd_buf(2) AND NOT rxd_buf(0) AND NOT rxd_buf(3) AND NOT rxd_buf(7))));


seg_data(5) <= NOT (((rxd_buf(4) AND rxd_buf(5) AND NOT rxd_buf(6) AND 
	rxd_buf(2) AND NOT rxd_buf(3) AND NOT rxd_buf(7))
	OR (rxd_buf(4) AND rxd_buf(5) AND NOT rxd_buf(6) AND 
	rxd_buf(0) AND NOT rxd_buf(3) AND NOT rxd_buf(7))
	OR (rxd_buf(1) AND NOT rxd_buf(4) AND NOT rxd_buf(5) AND 
	rxd_buf(6) AND NOT rxd_buf(2) AND NOT rxd_buf(3) AND NOT rxd_buf(7))
	OR (NOT rxd_buf(1) AND rxd_buf(4) AND rxd_buf(5) AND 
	NOT rxd_buf(6) AND NOT rxd_buf(2) AND NOT rxd_buf(0) AND NOT rxd_buf(7))
	OR (NOT rxd_buf(1) AND NOT rxd_buf(4) AND NOT rxd_buf(5) AND 
	rxd_buf(6) AND rxd_buf(0) AND NOT rxd_buf(3) AND NOT rxd_buf(7))));


seg_data(6) <= NOT (((clkbaud8x.EXP)
	OR (rxd_buf(4) AND rxd_buf(5) AND NOT rxd_buf(6) AND 
	NOT rxd_buf(2) AND NOT rxd_buf(3) AND NOT rxd_buf(7))
	OR (rxd_buf(1) AND rxd_buf(4) AND rxd_buf(5) AND 
	NOT rxd_buf(6) AND rxd_buf(0) AND NOT rxd_buf(3) AND NOT rxd_buf(7))
	OR (NOT rxd_buf(1) AND rxd_buf(4) AND rxd_buf(5) AND 
	NOT rxd_buf(6) AND NOT rxd_buf(2) AND NOT rxd_buf(0) AND NOT rxd_buf(7))
	OR (NOT rxd_buf(1) AND rxd_buf(4) AND rxd_buf(5) AND 
	NOT rxd_buf(6) AND NOT rxd_buf(0) AND NOT rxd_buf(3) AND NOT rxd_buf(7))
	OR (NOT rxd_buf(1) AND NOT rxd_buf(4) AND NOT rxd_buf(5) AND 
	rxd_buf(6) AND rxd_buf(0) AND NOT rxd_buf(3) AND NOT rxd_buf(7))));


seg_data(7) <= NOT (((state_rec(1).EXP)
	OR (rxd_buf(1) AND rxd_buf(4) AND rxd_buf(5) AND 
	NOT rxd_buf(6) AND NOT rxd_buf(3) AND NOT rxd_buf(7))
	OR (rxd_buf(1) AND NOT rxd_buf(4) AND NOT rxd_buf(5) AND 
	rxd_buf(6) AND rxd_buf(2) AND NOT rxd_buf(3) AND NOT rxd_buf(7))
	OR (rxd_buf(1) AND NOT rxd_buf(4) AND NOT rxd_buf(5) AND 
	rxd_buf(6) AND NOT rxd_buf(0) AND NOT rxd_buf(3) AND NOT rxd_buf(7))
	OR (NOT rxd_buf(1) AND rxd_buf(4) AND rxd_buf(5) AND 
	NOT rxd_buf(6) AND NOT rxd_buf(2) AND NOT rxd_buf(0) AND NOT rxd_buf(7))
	OR (rxd_buf(4) AND rxd_buf(5) AND NOT rxd_buf(6) AND 
	rxd_buf(2) AND rxd_buf(0) AND NOT rxd_buf(3) AND NOT rxd_buf(7))));

FTCPE_send_state0: FTCPE port map (send_state(0),'1',clkbaud8x,NOT rst,'0',send_state_CE(0));
send_state_CE(0) <= (state_tras(2) AND state_tras(1) AND state_tras(3) AND 
	state_tras(0) AND key_entry2 AND div8_tras_reg(0) AND div8_tras_reg(1) AND 
	div8_tras_reg(2));

FTCPE_send_state1: FTCPE port map (send_state(1),key_entry2.EXP,clkbaud8x,NOT rst,'0',send_state_CE(1));
send_state_CE(1) <= (state_tras(2) AND state_tras(1) AND state_tras(3) AND 
	state_tras(0) AND key_entry2 AND div8_tras_reg(0) AND div8_tras_reg(1) AND 
	div8_tras_reg(2));

FTCPE_send_state2: FTCPE port map (send_state(2),send_state_T(2),clkbaud8x,NOT rst,'0',send_state_CE(2));
send_state_T(2) <= (send_state(1) AND send_state(0));
send_state_CE(2) <= (state_tras(2) AND state_tras(1) AND state_tras(3) AND 
	state_tras(0) AND key_entry2 AND div8_tras_reg(0) AND div8_tras_reg(1) AND 
	div8_tras_reg(2));

FTCPE_start_delaycnt: FTCPE port map (start_delaycnt,start_delaycnt_T,clk,NOT rst,'0');
start_delaycnt_T <= ((start_delaycnt AND NOT cnt_delay(0) AND cnt_delay(10) AND 
	cnt_delay(12) AND cnt_delay(13) AND cnt_delay(18) AND cnt_delay(8) AND 
	NOT cnt_delay(11) AND NOT cnt_delay(14) AND NOT cnt_delay(15) AND NOT cnt_delay(16) AND 
	NOT cnt_delay(17) AND cnt_delay(19) AND NOT cnt_delay(1) AND NOT cnt_delay(2) AND 
	NOT cnt_delay(3) AND NOT cnt_delay(4) AND NOT cnt_delay(5) AND NOT cnt_delay(6) AND 
	NOT cnt_delay(7) AND NOT cnt_delay(9))
	OR (NOT key_input AND NOT start_delaycnt AND NOT cnt_delay(0) AND 
	NOT cnt_delay(10) AND NOT cnt_delay(12) AND NOT cnt_delay(13) AND NOT cnt_delay(18) AND 
	NOT cnt_delay(8) AND NOT cnt_delay(11) AND NOT cnt_delay(14) AND NOT cnt_delay(15) AND 
	NOT cnt_delay(16) AND NOT cnt_delay(17) AND NOT cnt_delay(19) AND NOT cnt_delay(1) AND 
	NOT cnt_delay(2) AND NOT cnt_delay(3) AND NOT cnt_delay(4) AND NOT cnt_delay(5) AND 
	NOT cnt_delay(6) AND NOT cnt_delay(7) AND NOT cnt_delay(9)));

FTCPE_state_rec0: FTCPE port map (state_rec(0),state_rec_T(0),clkbaud8x,NOT rst,'0');
state_rec_T(0) <= ((en_6_OBUF$BUF2.EXP)
	OR (NOT state_rec(0) AND NOT state_rec(1) AND NOT state_rec(2) AND 
	NOT state_rec(3) AND recstart_tmp)
	OR (state_rec(2) AND NOT state_rec(3) AND div8_rec_reg(0) AND 
	div8_rec_reg(1) AND div8_rec_reg(2))
	OR (NOT state_rec(1) AND NOT state_rec(2) AND state_rec(3) AND 
	div8_rec_reg(0) AND div8_rec_reg(1) AND div8_rec_reg(2)));

FTCPE_state_rec1: FTCPE port map (state_rec(1),state_rec_T(1),clkbaud8x,NOT rst,'0');
state_rec_T(1) <= (state_rec(0) AND NOT state_rec(3) AND div8_rec_reg(0) AND 
	div8_rec_reg(1) AND div8_rec_reg(2));

FTCPE_state_rec2: FTCPE port map (state_rec(2),state_rec_T(2),clkbaud8x,NOT rst,'0');
state_rec_T(2) <= (state_rec(0) AND state_rec(1) AND NOT state_rec(3) AND 
	div8_rec_reg(0) AND div8_rec_reg(1) AND div8_rec_reg(2));

FTCPE_state_rec3: FTCPE port map (state_rec(3),state_rec_T(3),clkbaud8x,NOT rst,'0');
state_rec_T(3) <= ((state_rec(0) AND state_rec(1) AND state_rec(2) AND 
	NOT state_rec(3) AND div8_rec_reg(0) AND div8_rec_reg(1) AND 
	div8_rec_reg(2))
	OR (state_rec(0) AND NOT state_rec(1) AND NOT state_rec(2) AND 
	state_rec(3) AND div8_rec_reg(0) AND div8_rec_reg(1) AND 
	div8_rec_reg(2)));

FTCPE_state_tras0: FTCPE port map (state_tras(0),state_tras_T(0),clkbaud8x,NOT rst,'0');
state_tras_T(0) <= ((NOT key_entry2)
	OR (EXP12_.EXP));

FTCPE_state_tras1: FTCPE port map (state_tras(1),state_tras_T(1),clkbaud8x,NOT rst,'0');
state_tras_T(1) <= (state_tras(0) AND key_entry2 AND div8_tras_reg(0) AND 
	div8_tras_reg(1) AND div8_tras_reg(2));

FTCPE_state_tras2: FTCPE port map (state_tras(2),state_tras_T(2),clkbaud8x,NOT rst,'0');
state_tras_T(2) <= (state_tras(1) AND state_tras(0) AND key_entry2 AND 
	div8_tras_reg(0) AND div8_tras_reg(1) AND div8_tras_reg(2));

FTCPE_state_tras3: FTCPE port map (state_tras(3),send_state(2).EXP,clkbaud8x,NOT rst,'0');

FTCPE_trasstart: FTCPE port map (trasstart,trasstart_T,clkbaud8x,NOT rst,'0',key_entry2);
trasstart_T <= ((EXP30_.EXP)
	OR (NOT state_tras(2) AND NOT state_tras(1) AND NOT state_tras(3) AND 
	NOT state_tras(0) AND NOT send_state(1) AND NOT trasstart)
	OR (NOT state_tras(2) AND NOT state_tras(1) AND NOT state_tras(3) AND 
	NOT state_tras(0) AND NOT send_state(2) AND NOT trasstart));

FDCPE_txd: FDCPE port map (txd,EXP25_.EXP,clkbaud8x,'0',NOT rst,key_entry2);

FDCPE_txd_buf0: FDCPE port map (txd_buf(0),txd_buf_D(0),clkbaud8x,NOT rst,'0');
txd_buf_D(0) <= ((EXP28_.EXP)
	OR (EXP29_.EXP)
	OR (key_entry2 AND NOT txd_buf(0) AND NOT div8_tras_reg(0))
	OR (key_entry2 AND NOT txd_buf(0) AND NOT div8_tras_reg(1))
	OR (state_tras(1) AND state_tras(3) AND NOT state_tras(0) AND 
	key_entry2 AND NOT txd_buf(0)));

FTCPE_txd_buf1: FTCPE port map (txd_buf(1),EXP21_.EXP,clkbaud8x,NOT rst,'0');

FDCPE_txd_buf2: FDCPE port map (txd_buf(2),txd_buf_D(2),clkbaud8x,NOT rst,'0');
txd_buf_D(2) <= ((EXP27_.EXP)
	OR (key_entry2 AND NOT txd_buf(2) AND NOT div8_tras_reg(0))
	OR (state_tras(1) AND state_tras(3) AND NOT state_tras(0) AND 
	key_entry2 AND NOT txd_buf(2)));

FDCPE_txd_buf3: FDCPE port map (txd_buf(3),txd_buf_D(3),clkbaud8x,NOT rst,'0');
txd_buf_D(3) <= ((EXP23_.EXP)
	OR (key_entry2 AND txd_buf(3) AND NOT div8_tras_reg(0)));

FTCPE_txd_buf4: FTCPE port map (txd_buf(4),txd_buf_T(4),clkbaud8x,NOT rst,'0');
txd_buf_T(4) <= ((EXP10_.EXP)
	OR (state_tras(1).EXP)
	OR (NOT key_entry2 AND NOT txd_buf(4) AND key_entry1)
	OR (state_tras(2) AND NOT state_tras(3) AND key_entry2 AND 
	txd_buf(4) AND NOT txd_buf(5) AND div8_tras_reg(0) AND div8_tras_reg(1) AND 
	div8_tras_reg(2))
	OR (state_tras(1) AND NOT state_tras(3) AND key_entry2 AND 
	txd_buf(4) AND NOT txd_buf(5) AND div8_tras_reg(0) AND div8_tras_reg(1) AND 
	div8_tras_reg(2)));

FTCPE_txd_buf5: FTCPE port map (txd_buf(5),txd_buf_T(5),clkbaud8x,NOT rst,'0');
txd_buf_T(5) <= ((state_tras(3).EXP)
	OR (EXP11_.EXP)
	OR (NOT key_entry2 AND NOT txd_buf(5) AND key_entry1)
	OR (state_tras(2) AND NOT state_tras(3) AND key_entry2 AND 
	txd_buf(5) AND div8_tras_reg(0) AND NOT txd_buf(6) AND div8_tras_reg(1) AND 
	div8_tras_reg(2))
	OR (NOT state_tras(3) AND state_tras(0) AND key_entry2 AND 
	txd_buf(5) AND div8_tras_reg(0) AND NOT txd_buf(6) AND div8_tras_reg(1) AND 
	div8_tras_reg(2)));

FTCPE_txd_buf6: FTCPE port map (txd_buf(6),txd_buf_T(6),clkbaud8x,NOT rst,'0');
txd_buf_T(6) <= ((EXP13_.EXP)
	OR (NOT key_entry2 AND NOT txd_buf(6) AND key_entry1)
	OR (state_tras(2) AND NOT state_tras(3) AND key_entry2 AND 
	div8_tras_reg(0) AND txd_buf(6) AND div8_tras_reg(1) AND div8_tras_reg(2)));

Register Legend:
 FDCPE (Q,D,C,CLR,PRE,CE); 
 FTCPE (Q,D,C,CLR,PRE,CE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC95144XL-10-TQ144


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 VCC                              73 VCC                           
  2 KPR                              74 KPR                           
  3 KPR                              75 KPR                           
  4 KPR                              76 KPR                           
  5 KPR                              77 rxd                           
  6 KPR                              78 KPR                           
  7 KPR                              79 txd                           
  8 VCC                              80 KPR                           
  9 KPR                              81 KPR                           
 10 KPR