uart.rpt

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

	NOT cnt_delay(9)));

FTCPE_cnt_delay19: FTCPE port map (cnt_delay(19),cnt_delay_T(19),clk,NOT rst,'0',start_delaycnt);
cnt_delay_T(19) <= ((cnt_delay(0) AND cnt_delay(10) AND cnt_delay(12) AND 
	cnt_delay(13) AND cnt_delay(18) AND cnt_delay(8) AND cnt_delay(11) AND 
	cnt_delay(14) AND cnt_delay(15) AND cnt_delay(16) AND cnt_delay(17) AND 
	cnt_delay(1) AND cnt_delay(2) AND cnt_delay(3) AND cnt_delay(4) AND 
	cnt_delay(5) AND cnt_delay(6) AND cnt_delay(7) AND cnt_delay(9))
	OR (NOT cnt_delay(0) AND cnt_delay(10) AND cnt_delay(12) AND 
	cnt_delay(13) AND cnt_delay(18) AND cnt_delay(8) AND NOT cnt_delay(11) AND 
	NOT cnt_delay(14) AND NOT cnt_delay(15) AND NOT cnt_delay(16) AND NOT cnt_delay(17) AND 
	cnt_delay(19) AND NOT cnt_delay(1) AND NOT cnt_delay(2) AND NOT cnt_delay(3) AND 
	NOT cnt_delay(4) AND NOT cnt_delay(5) AND NOT cnt_delay(6) AND NOT cnt_delay(7) AND 
	NOT cnt_delay(9)));

FTCPE_div8_rec_reg0: FTCPE port map (div8_rec_reg(0),'1',clkbaud8x,NOT rst,'0',recstart);

FTCPE_div8_rec_reg1: FTCPE port map (div8_rec_reg(1),div8_rec_reg(0),clkbaud8x,NOT rst,'0',recstart);

FTCPE_div8_rec_reg2: FTCPE port map (div8_rec_reg(2),div8_rec_reg_T(2),clkbaud8x,NOT rst,'0',recstart);
div8_rec_reg_T(2) <= (div8_rec_reg(0) AND div8_rec_reg(1));

FTCPE_div8_tras_reg0: FTCPE port map (div8_tras_reg(0),'1',clkbaud8x,NOT rst,'0',trasstart);

FTCPE_div8_tras_reg1: FTCPE port map (div8_tras_reg(1),div8_tras_reg(0),clkbaud8x,NOT rst,'0',trasstart);

FTCPE_div8_tras_reg2: FTCPE port map (div8_tras_reg(2),div8_tras_reg_T(2),clkbaud8x,NOT rst,'0',trasstart);
div8_tras_reg_T(2) <= (div8_tras_reg(0) AND div8_tras_reg(1));

FTCPE_div_reg0: FTCPE port map (div_reg(0),'1',clk,NOT rst,'0');

FTCPE_div_reg1: FTCPE port map (div_reg(1),div_reg(0),clk,NOT rst,'0');

FTCPE_div_reg2: FTCPE port map (div_reg(2),div_reg_T(2),clk,NOT rst,'0');
div_reg_T(2) <= ((NOT div_reg(0))
	OR (NOT div_reg(1))
	OR (NOT div_reg(10) AND NOT div_reg(11) AND NOT div_reg(12) AND 
	NOT div_reg(13) AND NOT div_reg(14) AND NOT div_reg(2) AND NOT div_reg(3) AND 
	NOT div_reg(4) AND NOT div_reg(5) AND NOT div_reg(6) AND NOT div_reg(7) AND 
	div_reg(8) AND NOT div_reg(9) AND NOT div_reg(15)));

FTCPE_div_reg3: FTCPE port map (div_reg(3),div_reg_T(3),clk,NOT rst,'0');
div_reg_T(3) <= (div_reg(0) AND div_reg(1) AND div_reg(2));

FTCPE_div_reg4: FTCPE port map (div_reg(4),div_reg_T(4),clk,NOT rst,'0');
div_reg_T(4) <= (div_reg(0) AND div_reg(1) AND div_reg(2) AND 
	div_reg(3));

FTCPE_div_reg5: FTCPE port map (div_reg(5),div_reg_T(5),clk,NOT rst,'0');
div_reg_T(5) <= (div_reg(0) AND div_reg(1) AND div_reg(2) AND 
	div_reg(3) AND div_reg(4));

FTCPE_div_reg6: FTCPE port map (div_reg(6),div_reg_T(6),clk,NOT rst,'0');
div_reg_T(6) <= (div_reg(0) AND div_reg(1) AND div_reg(2) AND 
	div_reg(3) AND div_reg(4) AND div_reg(5));

FTCPE_div_reg7: FTCPE port map (div_reg(7),div_reg_T(7),clk,NOT rst,'0');
div_reg_T(7) <= (div_reg(0) AND div_reg(1) AND div_reg(2) AND 
	div_reg(3) AND div_reg(4) AND div_reg(5) AND div_reg(6));

FTCPE_div_reg8: FTCPE port map (div_reg(8),div_reg_T(8),clk,NOT rst,'0');
div_reg_T(8) <= ((div_reg(0) AND div_reg(1) AND div_reg(2) AND 
	div_reg(3) AND div_reg(4) AND div_reg(5) AND div_reg(6) AND 
	div_reg(7))
	OR (div_reg(0) AND NOT div_reg(10) AND NOT div_reg(11) AND 
	NOT div_reg(12) AND NOT div_reg(13) AND NOT div_reg(14) AND div_reg(1) AND 
	NOT div_reg(2) AND NOT div_reg(3) AND NOT div_reg(4) AND NOT div_reg(5) AND 
	NOT div_reg(6) AND NOT div_reg(7) AND div_reg(8) AND NOT div_reg(9) AND 
	NOT div_reg(15)));

FTCPE_div_reg9: FTCPE port map (div_reg(9),div_reg_T(9),clk,NOT rst,'0');
div_reg_T(9) <= (div_reg(0) AND div_reg(1) AND div_reg(2) AND 
	div_reg(3) AND div_reg(4) AND div_reg(5) AND div_reg(6) AND 
	div_reg(7) AND div_reg(8));

FTCPE_div_reg10: FTCPE port map (div_reg(10),div_reg_T(10),clk,NOT rst,'0');
div_reg_T(10) <= (div_reg(0) AND div_reg(1) AND div_reg(2) AND 
	div_reg(3) AND div_reg(4) AND div_reg(5) AND div_reg(6) AND 
	div_reg(7) AND div_reg(8) AND div_reg(9));

FTCPE_div_reg11: FTCPE port map (div_reg(11),div_reg_T(11),clk,NOT rst,'0');
div_reg_T(11) <= (div_reg(0) AND div_reg(10) AND div_reg(1) AND 
	div_reg(2) AND div_reg(3) AND div_reg(4) AND div_reg(5) AND 
	div_reg(6) AND div_reg(7) AND div_reg(8) AND div_reg(9));

FTCPE_div_reg12: FTCPE port map (div_reg(12),div_reg_T(12),clk,NOT rst,'0');
div_reg_T(12) <= (div_reg(0) AND div_reg(10) AND div_reg(11) AND 
	div_reg(1) AND div_reg(2) AND div_reg(3) AND div_reg(4) AND 
	div_reg(5) AND div_reg(6) AND div_reg(7) AND div_reg(8) AND 
	div_reg(9));

FTCPE_div_reg13: FTCPE port map (div_reg(13),div_reg_T(13),clk,NOT rst,'0');
div_reg_T(13) <= (div_reg(0) AND div_reg(10) AND div_reg(11) AND 
	div_reg(12) AND div_reg(1) AND div_reg(2) AND div_reg(3) AND 
	div_reg(4) AND div_reg(5) AND div_reg(6) AND div_reg(7) AND 
	div_reg(8) AND div_reg(9));

FTCPE_div_reg14: FTCPE port map (div_reg(14),div_reg_T(14),clk,NOT rst,'0');
div_reg_T(14) <= (div_reg(0) AND div_reg(10) AND div_reg(11) AND 
	div_reg(12) AND div_reg(13) AND div_reg(1) AND div_reg(2) AND 
	div_reg(3) AND div_reg(4) AND div_reg(5) AND div_reg(6) AND 
	div_reg(7) AND div_reg(8) AND div_reg(9));

FTCPE_div_reg15: FTCPE port map (div_reg(15),div_reg_T(15),clk,NOT rst,'0');
div_reg_T(15) <= (div_reg(0) AND div_reg(10) AND div_reg(11) AND 
	div_reg(12) AND div_reg(13) AND div_reg(14) AND div_reg(1) AND 
	div_reg(2) AND div_reg(3) AND div_reg(4) AND div_reg(5) AND 
	div_reg(6) AND div_reg(7) AND div_reg(8) AND div_reg(9));


en(0) <= en_7_OBUF.EXP;


en(1) <= '1';


en(2) <= '1';


en(3) <= '1';


en(4) <= '1';


en(5) <= '1';


en(6) <= '1';


en(7) <= '0';

FDCPE_key_entry1: FDCPE port map (key_entry1,key_entry1_D,clk,NOT rst,'0');
key_entry1_D <= ((NOT key_entry2 AND key_entry1)
	OR (NOT key_input AND NOT key_entry2 AND NOT cnt_delay(0) AND 
	cnt_delay(10) AND cnt_delay(12) AND cnt_delay(13) AND cnt_delay(18) AND 
	cnt_delay(8) AND NOT cnt_delay(11) AND NOT cnt_delay(14) AND NOT cnt_delay(15) AND 
	NOT cnt_delay(16) AND NOT cnt_delay(17) AND cnt_delay(19) AND NOT cnt_delay(1) AND 
	NOT cnt_delay(2) AND NOT cnt_delay(3) AND NOT cnt_delay(4) AND NOT cnt_delay(5) AND 
	NOT cnt_delay(6) AND NOT cnt_delay(7) AND NOT cnt_delay(9)));

FTCPE_key_entry2: FTCPE port map (key_entry2,key_entry2_T,clkbaud8x,NOT rst,'0');
key_entry2_T <= ((NOT key_entry2 AND key_entry1)
	OR (NOT state_tras(2) AND NOT state_tras(1) AND NOT state_tras(3) AND 
	NOT state_tras(0) AND key_entry2 AND send_state(1) AND send_state(2) AND 
	send_state(0)));

FTCPE_recstart: FTCPE port map (recstart,recstart_T,clkbaud8x,NOT rst,'0');
recstart_T <= ((NOT state_rec(0) AND NOT state_rec(1) AND NOT state_rec(2) AND 
	NOT state_rec(3) AND recstart_tmp AND NOT recstart)
	OR (state_rec(0) AND NOT state_rec(1) AND NOT state_rec(2) AND 
	state_rec(3) AND div8_rec_reg(0) AND div8_rec_reg(1) AND recstart AND 
	div8_rec_reg(2)));

FTCPE_recstart_tmp: FTCPE port map (recstart_tmp,recstart_tmp_T,clkbaud8x,NOT rst,'0');
recstart_tmp_T <= ((NOT state_rec(0) AND NOT state_rec(1) AND NOT state_rec(2) AND 
	NOT state_rec(3) AND recstart_tmp)
	OR (NOT state_rec(0) AND NOT state_rec(1) AND NOT state_rec(2) AND 
	NOT state_rec(3) AND NOT rxd_reg1 AND rxd_reg2));

FTCPE_rxd_buf0: FTCPE port map (rxd_buf(0),rxd_buf_T(0),clkbaud8x,NOT rst,'0');
rxd_buf_T(0) <= ((EXP17_.EXP)
	OR (NOT rxd_buf(1) AND rxd_buf(0) AND state_rec(0) AND 
	NOT state_rec(3) AND div8_rec_reg(0) AND div8_rec_reg(1) AND 
	div8_rec_reg(2))
	OR (NOT rxd_buf(1) AND rxd_buf(0) AND state_rec(1) AND 
	NOT state_rec(3) AND div8_rec_reg(0) AND div8_rec_reg(1) AND 
	div8_rec_reg(2))
	OR (NOT rxd_buf(1) AND rxd_buf(0) AND state_rec(2) AND 
	NOT state_rec(3) AND div8_rec_reg(0) AND div8_rec_reg(1) AND 
	div8_rec_reg(2)));

FTCPE_rxd_buf1: FTCPE port map (rxd_buf(1),rxd_buf_T(1),clkbaud8x,NOT rst,'0');
rxd_buf_T(1) <= ((EXP16_.EXP)
	OR (rxd_buf(1) AND NOT rxd_buf(2) AND state_rec(0) AND 
	NOT state_rec(3) AND div8_rec_reg(0) AND div8_rec_reg(1) AND 
	div8_rec_reg(2))
	OR (rxd_buf(1) AND NOT rxd_buf(2) AND state_rec(1) AND 
	NOT state_rec(3) AND div8_rec_reg(0) AND div8_rec_reg(1) AND 
	div8_rec_reg(2))
	OR (rxd_buf(1) AND NOT rxd_buf(2) AND state_rec(2) AND 
	NOT state_rec(3) AND div8_rec_reg(0) AND div8_rec_reg(1) AND 
	div8_rec_reg(2)));

FTCPE_rxd_buf2: FTCPE port map (rxd_buf(2),rxd_buf_T(2),clkbaud8x,NOT rst,'0');
rxd_buf_T(2) <= ((EXP18_.EXP)
	OR (rxd_buf(2) AND NOT rxd_buf(3) AND state_rec(0) AND 
	NOT state_rec(3) AND div8_rec_reg(0) AND div8_rec_reg(1) AND 
	div8_rec_reg(2))
	OR (rxd_buf(2) AND NOT rxd_buf(3) AND state_rec(1) AND 
	NOT state_rec(3) AND div8_rec_reg(0) AND div8_rec_reg(1) AND 
	div8_rec_reg(2))
	OR (rxd_buf(2) AND NOT rxd_buf(3) AND state_rec(2) AND 
	NOT state_rec(3) AND div8_rec_reg(0) AND div8_rec_reg(1) AND 
	div8_rec_reg(2)));

FTCPE_rxd_buf3: FTCPE port map (rxd_buf(3),rxd_buf_T(3),clkbaud8x,NOT rst,'0');
rxd_buf_T(3) <= ((en_6_OBUF$BUF6.EXP)
	OR (NOT rxd_buf(4) AND rxd_buf(3) AND state_rec(0) AND 
	NOT state_rec(3) AND div8_rec_reg(0) AND div8_rec_reg(1) AND 
	div8_rec_reg(2))
	OR (NOT rxd_buf(4) AND rxd_buf(3) AND state_rec(1) AND 
	NOT state_rec(3) AND div8_rec_reg(0) AND div8_rec_reg(1) AND 
	div8_rec_reg(2))
	OR (NOT rxd_buf(4) AND rxd_buf(3) AND state_rec(2) AND 
	NOT state_rec(3) AND div8_rec_reg(0) AND div8_rec_reg(1) AND 
	div8_rec_reg(2)));

FTCPE_rxd_buf4: FTCPE port map (rxd_buf(4),rxd_buf_T(4),clkbaud8x,NOT rst,'0');
rxd_buf_T(4) <= ((rxd_buf(5).EXP)
	OR (en_6_OBUF$BUF5.EXP)
	OR (rxd_buf(4) AND NOT rxd_buf(5) AND state_rec(0) AND 
	NOT state_rec(3) AND div8_rec_reg(0) AND div8_rec_reg(1) AND 
	div8_rec_reg(2))
	OR (rxd_buf(4) AND NOT rxd_buf(5) AND state_rec(1) AND 
	NOT state_rec(3) AND div8_rec_reg(0) AND div8_rec_reg(1) AND 
	div8_rec_reg(2))
	OR (rxd_buf(4) AND NOT rxd_buf(5) AND state_rec(2) AND 
	NOT state_rec(3) AND div8_rec_reg(0) AND div8_rec_reg(1) AND 
	div8_rec_reg(2)));

FTCPE_rxd_buf5: FTCPE port map (rxd_buf(5),rxd_buf_T(5),clkbaud8x,NOT rst,'0');
rxd_buf_T(5) <= ((EXP15_.EXP)
	OR (rxd_buf(5) AND NOT rxd_buf(6) AND state_rec(0) AND 
	NOT state_rec(3) AND div8_rec_reg(0) AND div8_rec_reg(1) AND 
	div8_rec_reg(2))
	OR (rxd_buf(5) AND NOT rxd_buf(6) AND state_rec(1) AND 
	NOT state_rec(3) AND div8_rec_reg(0) AND div8_rec_reg(1) AND 
	div8_rec_reg(2)));

FTCPE_rxd_buf6: FTCPE port map (rxd_buf(6),rxd_buf_T(6),clkbaud8x,NOT rst,'0');
rxd_buf_T(6) <= ((EXP14_.EXP)
	OR (rxd_buf(6) AND NOT rxd_buf(7) AND state_rec(0) AND 
	NOT state_rec(3) AND div8_rec_reg(0) AND div8_rec_reg(1) AND 
	div8_rec_reg(2))
	OR (rxd_buf(6) AND NOT rxd_buf(7) AND state_rec(1) AND 
	NOT state_rec(3) AND div8_rec_reg(0) AND div8_rec_reg(1) AND 
	div8_rec_reg(2)));

FTCPE_rxd_buf7: FTCPE port map (rxd_buf(7),rxd_buf_T(7),clkbaud8x,NOT rst,'0');
rxd_buf_T(7) <= ((state_rec(2).EXP)
	OR (en_6_OBUF$BUF1.EXP)
	OR (rxd_buf(7) AND state_rec(0) AND NOT state_rec(3) AND 
	div8_rec_reg(0) AND div8_rec_reg(1) AND div8_rec_reg(2) AND NOT rxd_reg2)
	OR (rxd_buf(7) AND state_rec(1) AND NOT state_rec(3) AND 
	div8_rec_reg(0) AND div8_rec_reg(1) AND div8_rec_reg(2) AND NOT rxd_reg2)