📄 uart.rpt
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Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
txd_buf<1> XXXXXXX.XXXXXX...XX..................... 15
txd_buf<3> XXXXXXXXXXXXXX.....XX................... 16
txd XXXX.XXXXXXXXXXXX....................... 16
txd_buf<2> XXXXXXXXXXXXXX....XX.................... 16
txd_buf<0> XXXXXXXXXXXXXX..XX...................... 16
trasstart XXXX.XXXXXXXXXX......................... 14
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB8 ***********************************
Number of function block inputs used/remaining: 29/25
Number of signals used by logic mapping into function block: 29
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
rxd_reg2 3 0 0 2 FB8_1 (b) (b)
rxd_reg1 3 0 0 2 FB8_2 91 I/O (b)
div_reg<9> 3 0 0 2 FB8_3 95 I/O (b)
div_reg<7> 3 0 0 2 FB8_4 97 I/O (b)
div_reg<6> 3 0 0 2 FB8_5 92 I/O (b)
div_reg<5> 3 0 0 2 FB8_6 93 I/O (b)
div_reg<4> 3 0 0 2 FB8_7 (b) (b)
div_reg<3> 3 0 0 2 FB8_8 94 I/O (b)
div_reg<15> 3 0 0 2 FB8_9 96 I/O (b)
div_reg<14> 3 0 0 2 FB8_10 101 I/O (b)
div_reg<13> 3 0 0 2 FB8_11 98 I/O (b)
div_reg<12> 3 0 0 2 FB8_12 100 I/O (b)
div_reg<11> 3 0 0 2 FB8_13 103 I/O (b)
div_reg<10> 3 0 0 2 FB8_14 102 I/O (b)
clkbaud8x 3 0 \/1 1 FB8_15 104 I/O (b)
seg_data<6> 6 1<- 0 0 FB8_16 107 I/O O
div_reg<8> 4 0 0 1 FB8_17 105 I/O (b)
div_reg<2> 5 0 0 0 FB8_18 (b) (b)
Signals Used by Logic in Function Block
1: clk 11: div_reg<2> 21: rxd_buf<0>
2: clkbaud8x 12: div_reg<3> 22: rxd_buf<1>
3: div_reg<0> 13: div_reg<4> 23: rxd_buf<2>
4: div_reg<10> 14: div_reg<5> 24: rxd_buf<3>
5: div_reg<11> 15: div_reg<6> 25: rxd_buf<4>
6: div_reg<12> 16: div_reg<7> 26: rxd_buf<5>
7: div_reg<13> 17: div_reg<8> 27: rxd_buf<6>
8: div_reg<14> 18: div_reg<9> 28: rxd_buf<7>
9: div_reg<15> 19: rst 29: rxd_reg1
10: div_reg<1> 20: rxd
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
rxd_reg2 .X................X.........X........... 3
rxd_reg1 .X................XX.................... 3
div_reg<9> X.X......XXXXXXXX.X..................... 11
div_reg<7> X.X......XXXXXX...X..................... 9
div_reg<6> X.X......XXXXX....X..................... 8
div_reg<5> X.X......XXXX.....X..................... 7
div_reg<4> X.X......XXX......X..................... 6
div_reg<3> X.X......XX.......X..................... 5
div_reg<15> X.XXXXXX.XXXXXXXXXX..................... 17
div_reg<14> X.XXXXX..XXXXXXXXXX..................... 16
div_reg<13> X.XXXX...XXXXXXXXXX..................... 15
div_reg<12> X.XXX....XXXXXXXXXX..................... 14
div_reg<11> X.XX.....XXXXXXXXXX..................... 13
div_reg<10> X.X......XXXXXXXXXX..................... 12
clkbaud8x X.XXXXXXXXXXXXXXXXX..................... 18
seg_data<6> ....................XXXXXXXX............ 8
div_reg<8> X.XXXXXXXXXXXXXXXXX..................... 18
div_reg<2> X.XXXXXXXXXXXXXXXXX..................... 18
0----+----1----+----2----+----3----+----4
0 0 0 0
******************************* Equations ********************************
********** Mapped Logic **********
FTCPE_clkbaud8x: FTCPE port map (clkbaud8x,'1',clk,NOT rst,'0',clkbaud8x_CE);
clkbaud8x_CE <= (div_reg(0) AND NOT div_reg(10) AND NOT div_reg(11) AND
NOT div_reg(12) AND NOT div_reg(13) AND NOT div_reg(14) AND div_reg(1) AND
NOT div_reg(2) AND NOT div_reg(3) AND NOT div_reg(4) AND NOT div_reg(5) AND
NOT div_reg(6) AND NOT div_reg(7) AND div_reg(8) AND NOT div_reg(9) AND
NOT div_reg(15));
FTCPE_cnt_delay0: FTCPE port map (cnt_delay(0),cnt_delay_T(0),clk,NOT rst,'0',start_delaycnt);
cnt_delay_T(0) <= (NOT cnt_delay(0) AND cnt_delay(10) AND cnt_delay(12) AND
cnt_delay(13) AND cnt_delay(18) AND cnt_delay(8) AND NOT cnt_delay(11) AND
NOT cnt_delay(14) AND NOT cnt_delay(15) AND NOT cnt_delay(16) AND NOT cnt_delay(17) AND
cnt_delay(19) AND NOT cnt_delay(1) AND NOT cnt_delay(2) AND NOT cnt_delay(3) AND
NOT cnt_delay(4) AND NOT cnt_delay(5) AND NOT cnt_delay(6) AND NOT cnt_delay(7) AND
NOT cnt_delay(9));
FTCPE_cnt_delay1: FTCPE port map (cnt_delay(1),cnt_delay(0),clk,NOT rst,'0',start_delaycnt);
FTCPE_cnt_delay2: FTCPE port map (cnt_delay(2),cnt_delay_T(2),clk,NOT rst,'0',start_delaycnt);
cnt_delay_T(2) <= (cnt_delay(0) AND cnt_delay(1));
FTCPE_cnt_delay3: FTCPE port map (cnt_delay(3),cnt_delay_T(3),clk,NOT rst,'0',start_delaycnt);
cnt_delay_T(3) <= (cnt_delay(0) AND cnt_delay(1) AND cnt_delay(2));
FTCPE_cnt_delay4: FTCPE port map (cnt_delay(4),cnt_delay_T(4),clk,NOT rst,'0',start_delaycnt);
cnt_delay_T(4) <= (cnt_delay(0) AND cnt_delay(1) AND cnt_delay(2) AND
cnt_delay(3));
FTCPE_cnt_delay5: FTCPE port map (cnt_delay(5),cnt_delay_T(5),clk,NOT rst,'0',start_delaycnt);
cnt_delay_T(5) <= (cnt_delay(0) AND cnt_delay(1) AND cnt_delay(2) AND
cnt_delay(3) AND cnt_delay(4));
FTCPE_cnt_delay6: FTCPE port map (cnt_delay(6),cnt_delay_T(6),clk,NOT rst,'0',start_delaycnt);
cnt_delay_T(6) <= (cnt_delay(0) AND cnt_delay(1) AND cnt_delay(2) AND
cnt_delay(3) AND cnt_delay(4) AND cnt_delay(5));
FTCPE_cnt_delay7: FTCPE port map (cnt_delay(7),cnt_delay_T(7),clk,NOT rst,'0',start_delaycnt);
cnt_delay_T(7) <= (cnt_delay(0) AND cnt_delay(1) AND cnt_delay(2) AND
cnt_delay(3) AND cnt_delay(4) AND cnt_delay(5) AND cnt_delay(6));
FTCPE_cnt_delay8: FTCPE port map (cnt_delay(8),cnt_delay_T(8),clk,NOT rst,'0',start_delaycnt);
cnt_delay_T(8) <= ((cnt_delay(0) AND cnt_delay(1) AND cnt_delay(2) AND
cnt_delay(3) AND cnt_delay(4) AND cnt_delay(5) AND cnt_delay(6) AND
cnt_delay(7))
OR (NOT cnt_delay(0) AND cnt_delay(10) AND cnt_delay(12) AND
cnt_delay(13) AND cnt_delay(18) AND cnt_delay(8) AND NOT cnt_delay(11) AND
NOT cnt_delay(14) AND NOT cnt_delay(15) AND NOT cnt_delay(16) AND NOT cnt_delay(17) AND
cnt_delay(19) AND NOT cnt_delay(1) AND NOT cnt_delay(2) AND NOT cnt_delay(3) AND
NOT cnt_delay(4) AND NOT cnt_delay(5) AND NOT cnt_delay(6) AND NOT cnt_delay(7) AND
NOT cnt_delay(9)));
FTCPE_cnt_delay9: FTCPE port map (cnt_delay(9),cnt_delay_T(9),clk,NOT rst,'0',start_delaycnt);
cnt_delay_T(9) <= (cnt_delay(0) AND cnt_delay(8) AND cnt_delay(1) AND
cnt_delay(2) AND cnt_delay(3) AND cnt_delay(4) AND cnt_delay(5) AND
cnt_delay(6) AND cnt_delay(7));
FTCPE_cnt_delay10: FTCPE port map (cnt_delay(10),cnt_delay_T(10),clk,NOT rst,'0',start_delaycnt);
cnt_delay_T(10) <= ((cnt_delay(0) AND cnt_delay(8) AND cnt_delay(1) AND
cnt_delay(2) AND cnt_delay(3) AND cnt_delay(4) AND cnt_delay(5) AND
cnt_delay(6) AND cnt_delay(7) AND cnt_delay(9))
OR (NOT cnt_delay(0) AND cnt_delay(10) AND cnt_delay(12) AND
cnt_delay(13) AND cnt_delay(18) AND cnt_delay(8) AND NOT cnt_delay(11) AND
NOT cnt_delay(14) AND NOT cnt_delay(15) AND NOT cnt_delay(16) AND NOT cnt_delay(17) AND
cnt_delay(19) AND NOT cnt_delay(1) AND NOT cnt_delay(2) AND NOT cnt_delay(3) AND
NOT cnt_delay(4) AND NOT cnt_delay(5) AND NOT cnt_delay(6) AND NOT cnt_delay(7) AND
NOT cnt_delay(9)));
FTCPE_cnt_delay11: FTCPE port map (cnt_delay(11),cnt_delay_T(11),clk,NOT rst,'0',start_delaycnt);
cnt_delay_T(11) <= (cnt_delay(0) AND cnt_delay(10) AND cnt_delay(8) AND
cnt_delay(1) AND cnt_delay(2) AND cnt_delay(3) AND cnt_delay(4) AND
cnt_delay(5) AND cnt_delay(6) AND cnt_delay(7) AND cnt_delay(9));
FTCPE_cnt_delay12: FTCPE port map (cnt_delay(12),cnt_delay_T(12),clk,NOT rst,'0',start_delaycnt);
cnt_delay_T(12) <= ((cnt_delay(0) AND cnt_delay(10) AND cnt_delay(8) AND
cnt_delay(11) AND cnt_delay(1) AND cnt_delay(2) AND cnt_delay(3) AND
cnt_delay(4) AND cnt_delay(5) AND cnt_delay(6) AND cnt_delay(7) AND
cnt_delay(9))
OR (NOT cnt_delay(0) AND cnt_delay(10) AND cnt_delay(12) AND
cnt_delay(13) AND cnt_delay(18) AND cnt_delay(8) AND NOT cnt_delay(11) AND
NOT cnt_delay(14) AND NOT cnt_delay(15) AND NOT cnt_delay(16) AND NOT cnt_delay(17) AND
cnt_delay(19) AND NOT cnt_delay(1) AND NOT cnt_delay(2) AND NOT cnt_delay(3) AND
NOT cnt_delay(4) AND NOT cnt_delay(5) AND NOT cnt_delay(6) AND NOT cnt_delay(7) AND
NOT cnt_delay(9)));
FTCPE_cnt_delay13: FTCPE port map (cnt_delay(13),cnt_delay_T(13),clk,NOT rst,'0',start_delaycnt);
cnt_delay_T(13) <= ((cnt_delay(0) AND cnt_delay(10) AND cnt_delay(12) AND
cnt_delay(8) AND cnt_delay(11) AND cnt_delay(1) AND cnt_delay(2) AND
cnt_delay(3) AND cnt_delay(4) AND cnt_delay(5) AND cnt_delay(6) AND
cnt_delay(7) AND cnt_delay(9))
OR (NOT cnt_delay(0) AND cnt_delay(10) AND cnt_delay(12) AND
cnt_delay(13) AND cnt_delay(18) AND cnt_delay(8) AND NOT cnt_delay(11) AND
NOT cnt_delay(14) AND NOT cnt_delay(15) AND NOT cnt_delay(16) AND NOT cnt_delay(17) AND
cnt_delay(19) AND NOT cnt_delay(1) AND NOT cnt_delay(2) AND NOT cnt_delay(3) AND
NOT cnt_delay(4) AND NOT cnt_delay(5) AND NOT cnt_delay(6) AND NOT cnt_delay(7) AND
NOT cnt_delay(9)));
FTCPE_cnt_delay14: FTCPE port map (cnt_delay(14),cnt_delay_T(14),clk,NOT rst,'0',start_delaycnt);
cnt_delay_T(14) <= (cnt_delay(0) AND cnt_delay(10) AND cnt_delay(12) AND
cnt_delay(13) AND cnt_delay(8) AND cnt_delay(11) AND cnt_delay(1) AND
cnt_delay(2) AND cnt_delay(3) AND cnt_delay(4) AND cnt_delay(5) AND
cnt_delay(6) AND cnt_delay(7) AND cnt_delay(9));
FTCPE_cnt_delay15: FTCPE port map (cnt_delay(15),cnt_delay_T(15),clk,NOT rst,'0',start_delaycnt);
cnt_delay_T(15) <= (cnt_delay(0) AND cnt_delay(10) AND cnt_delay(12) AND
cnt_delay(13) AND cnt_delay(8) AND cnt_delay(11) AND cnt_delay(14) AND
cnt_delay(1) AND cnt_delay(2) AND cnt_delay(3) AND cnt_delay(4) AND
cnt_delay(5) AND cnt_delay(6) AND cnt_delay(7) AND cnt_delay(9));
FTCPE_cnt_delay16: FTCPE port map (cnt_delay(16),cnt_delay_T(16),clk,NOT rst,'0',start_delaycnt);
cnt_delay_T(16) <= (cnt_delay(0) AND cnt_delay(10) AND cnt_delay(12) AND
cnt_delay(13) AND cnt_delay(8) AND cnt_delay(11) AND cnt_delay(14) AND
cnt_delay(15) AND cnt_delay(1) AND cnt_delay(2) AND cnt_delay(3) AND
cnt_delay(4) AND cnt_delay(5) AND cnt_delay(6) AND cnt_delay(7) AND
cnt_delay(9));
FTCPE_cnt_delay17: FTCPE port map (cnt_delay(17),cnt_delay_T(17),clk,NOT rst,'0',start_delaycnt);
cnt_delay_T(17) <= (cnt_delay(0) AND cnt_delay(10) AND cnt_delay(12) AND
cnt_delay(13) AND cnt_delay(8) AND cnt_delay(11) AND cnt_delay(14) AND
cnt_delay(15) AND cnt_delay(16) AND cnt_delay(1) AND cnt_delay(2) AND
cnt_delay(3) AND cnt_delay(4) AND cnt_delay(5) AND cnt_delay(6) AND
cnt_delay(7) AND cnt_delay(9));
FTCPE_cnt_delay18: FTCPE port map (cnt_delay(18),cnt_delay_T(18),clk,NOT rst,'0',start_delaycnt);
cnt_delay_T(18) <= ((cnt_delay(0) AND cnt_delay(10) AND cnt_delay(12) AND
cnt_delay(13) AND cnt_delay(8) AND cnt_delay(11) AND cnt_delay(14) AND
cnt_delay(15) AND cnt_delay(16) AND cnt_delay(17) AND cnt_delay(1) AND
cnt_delay(2) AND cnt_delay(3) AND cnt_delay(4) AND cnt_delay(5) AND
cnt_delay(6) AND cnt_delay(7) AND cnt_delay(9))
OR (NOT cnt_delay(0) AND cnt_delay(10) AND cnt_delay(12) AND
cnt_delay(13) AND cnt_delay(18) AND cnt_delay(8) AND NOT cnt_delay(11) AND
NOT cnt_delay(14) AND NOT cnt_delay(15) AND NOT cnt_delay(16) AND NOT cnt_delay(17) AND
cnt_delay(19) AND NOT cnt_delay(1) AND NOT cnt_delay(2) AND NOT cnt_delay(3) AND
NOT cnt_delay(4) AND NOT cnt_delay(5) AND NOT cnt_delay(6) AND NOT cnt_delay(7) AND
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