⭐ 欢迎来到虫虫下载站! | 📦 资源下载 📁 资源专辑 ℹ️ 关于我们
⭐ 虫虫下载站

📄 uart.rpt

📁 Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档
💻 RPT
📖 第 1 页 / 共 5 页
字号:
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0   \/5   0     FB2_1   142   I/O     (b)
txd_buf<4>           13       8<-   0   0     FB2_2   143   GSR/I/O (b)
state_tras<1>         3       0   /\2   0     FB2_3         (b)     (b)
send_state<0>         3       0     0   2     FB2_4   4     I/O     (b)
div8_tras_reg<0>      3       0     0   2     FB2_5   2     GTS/I/O (b)
send_state<2>         4       0   \/1   0     FB2_6   3     GTS/I/O (b)
state_tras<3>         3       1<- \/3   0     FB2_7         (b)     (b)
txd_buf<5>           15      10<-   0   0     FB2_8   5     GTS/I/O (b)
(unused)              0       0   /\5   0     FB2_9   6     GTS/I/O (b)
send_state<1>         4       1<- /\2   0     FB2_10  7     I/O     (b)
key_entry2            4       0   /\1   0     FB2_11  9     I/O     (b)
state_tras<2>         3       0     0   2     FB2_12  10    I/O     (b)
div8_tras_reg<2>      4       0     0   1     FB2_13  12    I/O     (b)
div8_tras_reg<1>      4       0     0   1     FB2_14  11    I/O     (b)
(unused)              0       0   \/5   0     FB2_15  13    I/O     (b)
state_tras<0>         8       5<- \/2   0     FB2_16  14    I/O     (b)
(unused)              0       0   \/5   0     FB2_17  15    I/O     (b)
txd_buf<6>           11       7<- \/1   0     FB2_18        (b)     (b)

Signals Used by Logic in Function Block
  1: clkbaud8x          7: rst               13: state_tras<2> 
  2: div8_tras_reg<0>   8: send_state<0>     14: state_tras<3> 
  3: div8_tras_reg<1>   9: send_state<1>     15: trasstart 
  4: div8_tras_reg<2>  10: send_state<2>     16: txd_buf<4> 
  5: key_entry1        11: state_tras<0>     17: txd_buf<5> 
  6: key_entry2        12: state_tras<1>     18: txd_buf<6> 

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
txd_buf<4>           XXXXXXX...XXXX.XX....................... 13
state_tras<1>        XXXX.XX...X............................. 7
send_state<0>        XXXX.XX...XXXX.......................... 10
div8_tras_reg<0>     X.....X.......X......................... 3
send_state<2>        XXXX.XXXX.XXXX.......................... 12
state_tras<3>        XXXX.XX...XXX........................... 9
txd_buf<5>           XXXXXXX.XXXXXX..XX...................... 15
send_state<1>        XXXX.XXX..XXXX.......................... 11
key_entry2           X...XXXXXXXXXX.......................... 11
state_tras<2>        XXXX.XX...XX............................ 8
div8_tras_reg<2>     XXX...X.......X......................... 5
div8_tras_reg<1>     XX....X.......X......................... 4
state_tras<0>        XXXX.XXXXXXXXXX......................... 14
txd_buf<6>           XXXXXXX.XXXXXX...X...................... 14
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB3  ***********************************
Number of function block inputs used/remaining:               10/44
Number of signals used by logic mapping into function block:  10
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB3_1   39    I/O     
(unused)              0       0     0   5     FB3_2   32    GCK/I/O 
(unused)              0       0     0   5     FB3_3   41    I/O     
(unused)              0       0     0   5     FB3_4   44    I/O     
(unused)              0       0     0   5     FB3_5   33    I/O     
(unused)              0       0     0   5     FB3_6   34    I/O     
(unused)              0       0     0   5     FB3_7   46    I/O     
(unused)              0       0     0   5     FB3_8   38    GCK/I/O 
(unused)              0       0     0   5     FB3_9   40    I/O     
(unused)              0       0     0   5     FB3_10  48    I/O     
(unused)              0       0     0   5     FB3_11  43    I/O     
div_reg<0>            2       0     0   3     FB3_12  45    I/O     (b)
div_reg<1>            3       0     0   2     FB3_13        (b)     (b)
div8_rec_reg<0>       3       0     0   2     FB3_14  49    I/O     (b)
cnt_delay<4>          4       0     0   1     FB3_15  50    I/O     (b)
cnt_delay<3>          4       0     0   1     FB3_16        (b)     (b)
cnt_delay<2>          4       0     0   1     FB3_17  51    I/O     (b)
cnt_delay<1>          4       0     0   1     FB3_18        (b)     (b)

Signals Used by Logic in Function Block
  1: clk                5: cnt_delay<2>       8: recstart 
  2: clkbaud8x          6: cnt_delay<3>       9: rst 
  3: cnt_delay<0>       7: div_reg<0>        10: start_delaycnt 
  4: cnt_delay<1>     

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
div_reg<0>           X.......X............................... 2
div_reg<1>           X.....X.X............................... 3
div8_rec_reg<0>      .X.....XX............................... 3
cnt_delay<4>         X.XXXX..XX.............................. 7
cnt_delay<3>         X.XXX...XX.............................. 6
cnt_delay<2>         X.XX....XX.............................. 5
cnt_delay<1>         X.X.....XX.............................. 4
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB4  ***********************************
Number of function block inputs used/remaining:               17/37
Number of signals used by logic mapping into function block:  17
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
seg_data<1>           6       1<-   0   0     FB4_1   118   I/O     O
en<2>                 0       0   /\1   4     FB4_2   126   I/O     O
en<6>                 0       0   \/1   4     FB4_3   133   I/O     O
(unused)              0       0   \/5   0     FB4_4         (b)     (b)
rxd_buf<6>           10       6<- \/1   0     FB4_5   128   I/O     I
(unused)              0       0   \/5   0     FB4_6   129   I/O     (b)
rxd_buf<5>           10       6<- \/1   0     FB4_7         (b)     (b)
rxd_buf<4>           10       5<-   0   0     FB4_8   130   I/O     (b)
en<1>                 0       0   /\4   1     FB4_9   131   I/O     O
rxd_buf<3>           10       5<-   0   0     FB4_10  135   I/O     (b)
en<0>                 1       1<- /\5   0     FB4_11  132   I/O     O
en<7>                 0       0   /\1   4     FB4_12  134   I/O     O
(unused)              0       0   \/5   0     FB4_13  137   I/O     (b)
rxd_buf<1>           10       5<-   0   0     FB4_14  136   I/O     (b)
(unused)              0       0   \/5   0     FB4_15  138   I/O     (b)
rxd_buf<0>           10       5<-   0   0     FB4_16  139   I/O     (b)
(unused)              0       0   \/5   0     FB4_17  140   I/O     (b)
rxd_buf<2>           10       5<-   0   0     FB4_18        (b)     (b)

Signals Used by Logic in Function Block
  1: clkbaud8x          7: rxd_buf<1>        13: rxd_buf<7> 
  2: div8_rec_reg<0>    8: rxd_buf<2>        14: state_rec<0> 
  3: div8_rec_reg<1>    9: rxd_buf<3>        15: state_rec<1> 
  4: div8_rec_reg<2>   10: rxd_buf<4>        16: state_rec<2> 
  5: rst               11: rxd_buf<5>        17: state_rec<3> 
  6: rxd_buf<0>        12: rxd_buf<6>       

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
seg_data<1>          .....XXXXXXXX........................... 8
en<2>                ........................................ 0
en<6>                ........................................ 0
rxd_buf<6>           XXXXX......XXXXXX....................... 11
rxd_buf<5>           XXXXX.....XX.XXXX....................... 11
rxd_buf<4>           XXXXX....XX..XXXX....................... 11
en<1>                ........................................ 0
rxd_buf<3>           XXXXX...XX...XXXX....................... 11
en<0>                ........................................ 0
en<7>                ........................................ 0
rxd_buf<1>           XXXXX.XX.....XXXX....................... 11
rxd_buf<0>           XXXXXXX......XXXX....................... 11
rxd_buf<2>           XXXXX..XX....XXXX....................... 11
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB5  ***********************************
Number of function block inputs used/remaining:               0/54
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB5_1         (b)     
(unused)              0       0     0   5     FB5_2   52    I/O     
(unused)              0       0     0   5     FB5_3   59    I/O     
(unused)              0       0     0   5     FB5_4         (b)     
(unused)              0       0     0   5     FB5_5   53    I/O     
(unused)              0       0     0   5     FB5_6   54    I/O     
(unused)              0       0     0   5     FB5_7   66    I/O     
(unused)              0       0     0   5     FB5_8   56    I/O     
(unused)              0       0     0   5     FB5_9   57    I/O     
(unused)              0       0     0   5     FB5_10  68    I/O     
(unused)              0       0     0   5     FB5_11  58    I/O     
(unused)              0       0     0   5     FB5_12  60    I/O     
(unused)              0       0     0   5     FB5_13  70    I/O     I
(unused)              0       0     0   5     FB5_14  61    I/O     
(unused)              0       0     0   5     FB5_15  64    I/O     
(unused)              0       0     0   5     FB5_16        (b)     
(unused)              0       0     0   5     FB5_17  69    I/O     
(unused)              0       0     0   5     FB5_18        (b)     
*********************************** FB6  ***********************************
Number of function block inputs used/remaining:               21/33
Number of signals used by logic mapping into function block:  21
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
state_rec<2>          3       0   /\1   1     FB6_1         (b)     (b)
seg_data<7>           7       2<-   0   0     FB6_2   106   I/O     O
state_rec<1>          3       0   /\2   0     FB6_3         (b)     (b)
seg_data<5>           5       0     0   0     FB6_4   111   I/O     O
state_rec<3>          4       0     0   1     FB6_5   110   I/O     (b)
recstart_tmp          4       0     0   1     FB6_6   112   I/O     (b)
recstart              4       0   \/1   0     FB6_7         (b)     (b)
seg_data<4>           7       2<-   0   0     FB6_8   113   I/O     O
seg_data<2>           6       2<- /\1   0     FB6_9   116   I/O     O
seg_data<3>           4       1<- /\2   0     FB6_10  115   I/O     O
seg_data<0>           0       0   /\1   4     FB6_11  119   I/O     O
en<3>                 0       0     0   5     FB6_12  120   I/O     O
div8_rec_reg<2>       4       0     0   1     FB6_13        (b)     (b)
div8_rec_reg<1>       4       0     0   1     FB6_14  121   I/O     (b)
en<4>                 0       0   \/2   3     FB6_15  124   I/O     O
state_rec<0>          7       2<-   0   0     FB6_16  117   I/O     (b)
en<5>                 0       0   \/4   1     FB6_17  125   I/O     O
rxd_buf<7>           10       5<-   0   0     FB6_18        (b)     (b)

Signals Used by Logic in Function Block
  1: clkbaud8x          8: rxd_buf<0>        15: rxd_buf<7> 
  2: div8_rec_reg<0>    9: rxd_buf<1>        16: rxd_reg1 
  3: div8_rec_reg<1>   10: rxd_buf<2>        17: rxd_reg2 
  4: div8_rec_reg<2>   11: rxd_buf<3>        18: state_rec<0> 
  5: recstart          12: rxd_buf<4>        19: state_rec<1> 
  6: recstart_tmp      13: rxd_buf<5>        20: state_rec<2> 
  7: rst               14: rxd_buf<6>        21: state_rec<3> 

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
state_rec<2>         XXXX..X..........XX.X................... 8
seg_data<7>          .......XXXXXXXX......................... 8
state_rec<1>         XXXX..X..........X..X................... 7
seg_data<5>          .......XXXXXXXX......................... 8
state_rec<3>         XXXX..X..........XXXX................... 9
recstart_tmp         X....XX........XXXXXX................... 9
recstart             XXXXXXX..........XXXX................... 11
seg_data<4>          .......XXXXXXXX......................... 8
seg_data<2>          .......XXXXXXXX......................... 8
seg_data<3>          .......XXXXXXXX......................... 8
seg_data<0>          ........................................ 0
en<3>                ........................................ 0
div8_rec_reg<2>      XXX.X.X................................. 5
div8_rec_reg<1>      XX..X.X................................. 4
en<4>                ........................................ 0
state_rec<0>         XXXX.XX..........XXXX................... 10
en<5>                ........................................ 0
rxd_buf<7>           XXXX..X.......X.XXXXX................... 11
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB7  ***********************************
Number of function block inputs used/remaining:               21/33
Number of signals used by logic mapping into function block:  21
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0   \/3   2     FB7_1         (b)     (b)
(unused)              0       0   \/5   0     FB7_2   71    I/O     I
(unused)              0       0   \/5   0     FB7_3   75    I/O     (b)
txd_buf<1>           15      13<- \/3   0     FB7_4         (b)     (b)
(unused)              0       0   \/5   0     FB7_5   74    I/O     (b)
(unused)              0       0   \/5   0     FB7_6   76    I/O     (b)
txd_buf<3>           16      13<- \/2   0     FB7_7   77    I/O     I
(unused)              0       0   \/5   0     FB7_8   78    I/O     (b)
(unused)              0       0   \/5   0     FB7_9   80    I/O     (b)
txd                  15      12<- \/2   0     FB7_10  79    I/O     O
(unused)              0       0   \/5   0     FB7_11  82    I/O     (b)
(unused)              0       0   \/5   0     FB7_12  85    I/O     (b)
txd_buf<2>           16      12<- \/1   0     FB7_13  81    I/O     (b)
(unused)              0       0   \/5   0     FB7_14  86    I/O     (b)
txd_buf<0>           16      11<-   0   0     FB7_15  87    I/O     (b)
(unused)              0       0   /\5   0     FB7_16  83    I/O     (b)
(unused)              0       0   \/5   0     FB7_17  88    I/O     (b)
trasstart            10       5<-   0   0     FB7_18        (b)     (b)

Signals Used by Logic in Function Block
  1: clkbaud8x          8: send_state<0>     15: trasstart 
  2: div8_tras_reg<0>   9: send_state<1>     16: txd 
  3: div8_tras_reg<1>  10: send_state<2>     17: txd_buf<0> 
  4: div8_tras_reg<2>  11: state_tras<0>     18: txd_buf<1> 
  5: key_entry1        12: state_tras<1>     19: txd_buf<2> 
  6: key_entry2        13: state_tras<2>     20: txd_buf<3> 
  7: rst               14: state_tras<3>     21: txd_buf<4> 

⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -