📄 uart.rpt
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cpldfit: version H.42 Xilinx Inc.
Fitter Report
Design Name: uart Date: 2-21-2006, 11:28AM
Device Used: XC95144XL-10-TQ144
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
94 /144 ( 65%) 481 /720 ( 67%) 142/432 ( 33%) 78 /144 ( 54%) 21 /117 ( 18%)
** Function Block Resources **
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 26/54 78/90 0/15
FB2 14/18 18/54 82/90 0/15
FB3 7/18 10/54 24/90 0/15
FB4 13/18 17/54 77/90 6/15
FB5 0/18 0/54 0/90 0/14
FB6 18/18* 21/54 72/90 9/13
FB7 6/18 21/54 88/90 1/15
FB8 18/18* 29/54 60/90 1/15
----- ----- ----- -----
94/144 142/432 481/720 17/117
* - Resource is exhausted
** Global Control Resources **
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 4 4 | I/O : 21 109
Output : 17 17 | GCK/IO : 0 3
Bidirectional : 0 0 | GTS/IO : 0 4
GCK : 0 0 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 21 21
** Power Data **
There are 94 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
************************* Summary of Mapped Logic ************************
** 17 Outputs **
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
seg_data<1> 6 8 FB4_1 118 I/O O STD FAST
en<2> 0 0 FB4_2 126 I/O O STD FAST
en<6> 0 0 FB4_3 133 I/O O STD FAST
en<1> 0 0 FB4_9 131 I/O O STD FAST
en<0> 1 0 FB4_11 132 I/O O STD FAST
en<7> 0 0 FB4_12 134 I/O O STD FAST
seg_data<7> 7 8 FB6_2 106 I/O O STD FAST
seg_data<5> 5 8 FB6_4 111 I/O O STD FAST
seg_data<4> 7 8 FB6_8 113 I/O O STD FAST
seg_data<2> 6 8 FB6_9 116 I/O O STD FAST
seg_data<3> 4 8 FB6_10 115 I/O O STD FAST
seg_data<0> 0 0 FB6_11 119 I/O O STD FAST
en<3> 0 0 FB6_12 120 I/O O STD FAST
en<4> 0 0 FB6_15 124 I/O O STD FAST
en<5> 0 0 FB6_17 125 I/O O STD FAST
txd 15 16 FB7_10 79 I/O O STD FAST RESET
seg_data<6> 6 8 FB8_16 107 I/O O STD FAST
** 77 Buried Nodes **
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
start_delaycnt 4 24 FB1_1 STD RESET
key_entry1 4 25 FB1_2 STD RESET
cnt_delay<9> 4 12 FB1_3 STD RESET
cnt_delay<7> 4 10 FB1_4 STD RESET
cnt_delay<6> 4 9 FB1_5 STD RESET
cnt_delay<5> 4 8 FB1_6 STD RESET
cnt_delay<17> 4 20 FB1_7 STD RESET
cnt_delay<16> 4 19 FB1_8 STD RESET
cnt_delay<15> 4 18 FB1_9 STD RESET
cnt_delay<14> 4 17 FB1_10 STD RESET
cnt_delay<11> 4 14 FB1_11 STD RESET
cnt_delay<0> 4 23 FB1_12 STD RESET
cnt_delay<8> 5 23 FB1_13 STD RESET
cnt_delay<19> 5 23 FB1_14 STD RESET
cnt_delay<18> 5 23 FB1_15 STD RESET
cnt_delay<13> 5 23 FB1_16 STD RESET
cnt_delay<12> 5 23 FB1_17 STD RESET
cnt_delay<10> 5 23 FB1_18 STD RESET
txd_buf<4> 13 13 FB2_2 STD RESET
state_tras<1> 3 7 FB2_3 STD RESET
send_state<0> 3 10 FB2_4 STD RESET
div8_tras_reg<0> 3 3 FB2_5 STD RESET
send_state<2> 4 12 FB2_6 STD RESET
state_tras<3> 3 9 FB2_7 STD RESET
txd_buf<5> 15 15 FB2_8 STD RESET
send_state<1> 4 11 FB2_10 STD RESET
key_entry2 4 11 FB2_11 STD RESET
state_tras<2> 3 8 FB2_12 STD RESET
div8_tras_reg<2> 4 5 FB2_13 STD RESET
div8_tras_reg<1> 4 4 FB2_14 STD RESET
state_tras<0> 8 14 FB2_16 STD RESET
txd_buf<6> 11 14 FB2_18 STD RESET
div_reg<0> 2 2 FB3_12 STD RESET
div_reg<1> 3 3 FB3_13 STD RESET
div8_rec_reg<0> 3 3 FB3_14 STD RESET
cnt_delay<4> 4 7 FB3_15 STD RESET
cnt_delay<3> 4 6 FB3_16 STD RESET
cnt_delay<2> 4 5 FB3_17 STD RESET
cnt_delay<1> 4 4 FB3_18 STD RESET
rxd_buf<6> 10 11 FB4_5 STD RESET
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
rxd_buf<5> 10 11 FB4_7 STD RESET
rxd_buf<4> 10 11 FB4_8 STD RESET
rxd_buf<3> 10 11 FB4_10 STD RESET
rxd_buf<1> 10 11 FB4_14 STD RESET
rxd_buf<0> 10 11 FB4_16 STD RESET
rxd_buf<2> 10 11 FB4_18 STD RESET
state_rec<2> 3 8 FB6_1 STD RESET
state_rec<1> 3 7 FB6_3 STD RESET
state_rec<3> 4 9 FB6_5 STD RESET
recstart_tmp 4 9 FB6_6 STD RESET
recstart 4 11 FB6_7 STD RESET
div8_rec_reg<2> 4 5 FB6_13 STD RESET
div8_rec_reg<1> 4 4 FB6_14 STD RESET
state_rec<0> 7 10 FB6_16 STD RESET
rxd_buf<7> 10 11 FB6_18 STD RESET
txd_buf<1> 15 15 FB7_4 STD RESET
txd_buf<3> 16 16 FB7_7 STD RESET
txd_buf<2> 16 16 FB7_13 STD RESET
txd_buf<0> 16 16 FB7_15 STD RESET
trasstart 10 14 FB7_18 STD RESET
rxd_reg2 3 3 FB8_1 STD RESET
rxd_reg1 3 3 FB8_2 STD RESET
div_reg<9> 3 11 FB8_3 STD RESET
div_reg<7> 3 9 FB8_4 STD RESET
div_reg<6> 3 8 FB8_5 STD RESET
div_reg<5> 3 7 FB8_6 STD RESET
div_reg<4> 3 6 FB8_7 STD RESET
div_reg<3> 3 5 FB8_8 STD RESET
div_reg<15> 3 17 FB8_9 STD RESET
div_reg<14> 3 16 FB8_10 STD RESET
div_reg<13> 3 15 FB8_11 STD RESET
div_reg<12> 3 14 FB8_12 STD RESET
div_reg<11> 3 13 FB8_13 STD RESET
div_reg<10> 3 12 FB8_14 STD RESET
clkbaud8x 3 18 FB8_15 STD RESET
div_reg<8> 4 18 FB8_17 STD RESET
div_reg<2> 5 18 FB8_18 STD RESET
** 4 Inputs **
Signal Loc Pin Pin Pin
Name No. Type Use
clk FB4_5 128 I/O I
key_input FB5_13 70 I/O I
rst FB7_2 71 I/O I
rxd FB7_7 77 I/O I
Legend:
Pin No. - ~ - User Assigned
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X - Signal used as input to the macrocell logic.
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 26/28
Number of signals used by logic mapping into function block: 26
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
start_delaycnt 4 0 0 1 FB1_1 23 I/O (b)
key_entry1 4 0 0 1 FB1_2 16 I/O (b)
cnt_delay<9> 4 0 0 1 FB1_3 17 I/O (b)
cnt_delay<7> 4 0 0 1 FB1_4 25 I/O (b)
cnt_delay<6> 4 0 0 1 FB1_5 19 I/O (b)
cnt_delay<5> 4 0 0 1 FB1_6 20 I/O (b)
cnt_delay<17> 4 0 0 1 FB1_7 (b) (b)
cnt_delay<16> 4 0 0 1 FB1_8 21 I/O (b)
cnt_delay<15> 4 0 0 1 FB1_9 22 I/O (b)
cnt_delay<14> 4 0 0 1 FB1_10 31 I/O (b)
cnt_delay<11> 4 0 0 1 FB1_11 24 I/O (b)
cnt_delay<0> 4 0 0 1 FB1_12 26 I/O (b)
cnt_delay<8> 5 0 0 0 FB1_13 (b) (b)
cnt_delay<19> 5 0 0 0 FB1_14 27 I/O (b)
cnt_delay<18> 5 0 0 0 FB1_15 28 I/O (b)
cnt_delay<13> 5 0 0 0 FB1_16 35 I/O (b)
cnt_delay<12> 5 0 0 0 FB1_17 30 GCK/I/O (b)
cnt_delay<10> 5 0 0 0 FB1_18 (b) (b)
Signals Used by Logic in Function Block
1: clk 10: cnt_delay<17> 19: cnt_delay<7>
2: cnt_delay<0> 11: cnt_delay<18> 20: cnt_delay<8>
3: cnt_delay<10> 12: cnt_delay<19> 21: cnt_delay<9>
4: cnt_delay<11> 13: cnt_delay<1> 22: key_entry1
5: cnt_delay<12> 14: cnt_delay<2> 23: key_entry2
6: cnt_delay<13> 15: cnt_delay<3> 24: key_input
7: cnt_delay<14> 16: cnt_delay<4> 25: rst
8: cnt_delay<15> 17: cnt_delay<5> 26: start_delaycnt
9: cnt_delay<16> 18: cnt_delay<6>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
start_delaycnt XXXXXXXXXXXXXXXXXXXXX..XXX.............. 24
key_entry1 XXXXXXXXXXXXXXXXXXXXXXXXX............... 25
cnt_delay<9> XX..........XXXXXXXX....XX.............. 12
cnt_delay<7> XX..........XXXXXX......XX.............. 10
cnt_delay<6> XX..........XXXXX.......XX.............. 9
cnt_delay<5> XX..........XXXX........XX.............. 8
cnt_delay<17> XXXXXXXXX...XXXXXXXXX...XX.............. 20
cnt_delay<16> XXXXXXXX....XXXXXXXXX...XX.............. 19
cnt_delay<15> XXXXXXX.....XXXXXXXXX...XX.............. 18
cnt_delay<14> XXXXXX......XXXXXXXXX...XX.............. 17
cnt_delay<11> XXX.........XXXXXXXXX...XX.............. 14
cnt_delay<0> XXXXXXXXXXXXXXXXXXXXX...XX.............. 23
cnt_delay<8> XXXXXXXXXXXXXXXXXXXXX...XX.............. 23
cnt_delay<19> XXXXXXXXXXXXXXXXXXXXX...XX.............. 23
cnt_delay<18> XXXXXXXXXXXXXXXXXXXXX...XX.............. 23
cnt_delay<13> XXXXXXXXXXXXXXXXXXXXX...XX.............. 23
cnt_delay<12> XXXXXXXXXXXXXXXXXXXXX...XX.............. 23
cnt_delay<10> XXXXXXXXXXXXXXXXXXXXX...XX.............. 23
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 18/36
Number of signals used by logic mapping into function block: 18
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