uart.syr

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

#      1-bit 4-to-1 multiplexer    : 2
#      4-bit 4-to-1 multiplexer    : 1
# Adders/Subtractors               : 2
#      20-bit adder                : 1
#      4-bit adder                 : 1
# Comparators                      : 5
#      3-bit comparator less       : 1
#      4-bit comparator greatequal : 1
#      4-bit comparator greater    : 1
#      4-bit comparator less       : 1
#      4-bit comparator lessequal  : 1

Cell Usage :
# BELS                             : 276
#      GND                         : 1
#      INV                         : 9
#      LUT1                        : 14
#      LUT1_L                      : 8
#      LUT2                        : 14
#      LUT2_D                      : 1
#      LUT2_L                      : 21
#      LUT3                        : 16
#      LUT3_D                      : 2
#      LUT3_L                      : 19
#      LUT4                        : 59
#      LUT4_D                      : 9
#      LUT4_L                      : 23
#      MUXCY                       : 39
#      MUXF5                       : 1
#      VCC                         : 1
#      XORCY                       : 39
# FlipFlops/Latches                : 78
#      FDC                         : 2
#      FDCE                        : 55
#      FDCPE                       : 20
#      FDPE                        : 1
# Clock Buffers                    : 2
#      BUFG                        : 1
#      BUFGP                       : 1
# IO Buffers                       : 20
#      IBUF                        : 3
#      OBUF                        : 17
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-6 

 Number of Slices:                     102  out of    768    13%  
 Number of Slice Flip Flops:            78  out of   1536     5%  
 Number of 4 input LUTs:               186  out of   1536    12%  
 Number of bonded IOBs:                 21  out of     96    21%  
 Number of GCLKs:                        2  out of      4    50%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clkbaud8x:Q                        | BUFG                   | 39    |
clk                                | BUFGP                  | 39    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 9.959ns (Maximum Frequency: 100.412MHz)
   Minimum input arrival time before clock: 6.036ns
   Maximum output required time after clock: 15.419ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clkbaud8x:Q'
  Clock period: 9.715ns (frequency: 102.934MHz)
  Total number of paths / destination ports: 658 / 75
-------------------------------------------------------------------------
Delay:               9.715ns (Levels of Logic = 4)
  Source:            state_tras_3 (FF)
  Destination:       txd_buf_0 (FF)
  Source Clock:      clkbaud8x:Q rising
  Destination Clock: clkbaud8x:Q rising

  Data Path: state_tras_3 to txd_buf_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q           15   1.085   2.430  state_tras_3 (state_tras_3)
     LUT4_D:I0->O          7   0.549   1.755  Ker501 (N50)
     LUT4_D:I1->LO         1   0.549   0.100  Ker1742 (N932)
     LUT4:I0->O            4   0.549   1.440  Ker01 (N0)
     LUT4_L:I2->LO         1   0.549   0.000  _n0014 (_n0014)
     FDCE:D                    0.709          txd_buf_6
    ----------------------------------------
    Total                      9.715ns (3.990ns logic, 5.725ns route)
                                       (41.1% logic, 58.9% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 9.959ns (frequency: 100.412MHz)
  Total number of paths / destination ports: 3264 / 61
-------------------------------------------------------------------------
Delay:               9.959ns (Levels of Logic = 19)
  Source:            div_reg_12 (FF)
  Destination:       div_reg_15 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: div_reg_12 to div_reg_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q            2   1.085   1.206  div_reg_12 (div_reg_12)
     LUT4:I0->O            1   0.549   1.035  _n001856 (CHOICE334)
     LUT4_D:I0->O         17   0.549   2.610  _n001869 (_n0018)
     LUT3_L:I0->LO         1   0.549   0.000  div_reg_inst_lut3_41 (div_reg_inst_lut3_4)
     MUXCY:S->O            1   0.659   0.000  div_reg_inst_cy_6 (div_reg_inst_cy_6)
     MUXCY:CI->O           1   0.042   0.000  div_reg_inst_cy_7 (div_reg_inst_cy_7)
     MUXCY:CI->O           1   0.042   0.000  div_reg_inst_cy_8 (div_reg_inst_cy_8)
     MUXCY:CI->O           1   0.042   0.000  div_reg_inst_cy_9 (div_reg_inst_cy_9)
     MUXCY:CI->O           1   0.042   0.000  div_reg_inst_cy_10 (div_reg_inst_cy_10)
     MUXCY:CI->O           1   0.042   0.000  div_reg_inst_cy_11 (div_reg_inst_cy_11)
     MUXCY:CI->O           1   0.042   0.000  div_reg_inst_cy_12 (div_reg_inst_cy_12)
     MUXCY:CI->O           1   0.042   0.000  div_reg_inst_cy_13 (div_reg_inst_cy_13)
     MUXCY:CI->O           1   0.042   0.000  div_reg_inst_cy_14 (div_reg_inst_cy_14)
     MUXCY:CI->O           1   0.042   0.000  div_reg_inst_cy_15 (div_reg_inst_cy_15)
     MUXCY:CI->O           1   0.042   0.000  div_reg_inst_cy_16 (div_reg_inst_cy_16)
     MUXCY:CI->O           1   0.042   0.000  div_reg_inst_cy_17 (div_reg_inst_cy_17)
     MUXCY:CI->O           1   0.042   0.000  div_reg_inst_cy_18 (div_reg_inst_cy_18)
     MUXCY:CI->O           1   0.042   0.000  div_reg_inst_cy_19 (div_reg_inst_cy_19)
     MUXCY:CI->O           0   0.042   0.000  div_reg_inst_cy_20 (div_reg_inst_cy_20)
     XORCY:CI->O           1   0.420   0.000  div_reg_inst_sum_19 (div_reg_inst_sum_19)
     FDCPE:D                   0.709          div_reg_15
    ----------------------------------------
    Total                      9.959ns (5.108ns logic, 4.851ns route)
                                       (51.3% logic, 48.7% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clkbaud8x:Q'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              2.520ns (Levels of Logic = 1)
  Source:            rxd (PAD)
  Destination:       rxd_reg1 (FF)
  Destination Clock: clkbaud8x:Q rising

  Data Path: rxd to rxd_reg1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.776   1.035  rxd_IBUF (rxd_IBUF)
     FDC:D                     0.709          rxd_reg1
    ----------------------------------------
    Total                      2.520ns (1.485ns logic, 1.035ns route)
                                       (58.9% logic, 41.1% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Offset:              6.036ns (Levels of Logic = 3)
  Source:            key_input (PAD)
  Destination:       start_delaycnt (FF)
  Destination Clock: clk rising

  Data Path: key_input to start_delaycnt
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             2   0.776   1.206  key_input_IBUF (key_input_IBUF)
     LUT3:I2->O            1   0.549   1.035  _n0152_SW1 (N902)
     LUT4:I3->O            1   0.549   1.035  _n01881 (_n0188)
     FDCE:CE                   0.886          key_entry1
    ----------------------------------------
    Total                      6.036ns (2.760ns logic, 3.276ns route)
                                       (45.7% logic, 54.3% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clkbaud8x:Q'
  Total number of paths / destination ports: 191 / 8
-------------------------------------------------------------------------
Offset:              15.419ns (Levels of Logic = 5)
  Source:            rxd_buf_1 (FF)
  Destination:       seg_data<7> (PAD)
  Source Clock:      clkbaud8x:Q rising

  Data Path: rxd_buf_1 to seg_data<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q            17   1.085   2.610  rxd_buf_1 (rxd_buf_1)
     LUT4:I3->O            1   0.549   1.035  Ker3427 (CHOICE87)
     LUT4:I0->O            1   0.549   1.035  Ker3432 (CHOICE89)
     LUT4:I2->O            7   0.549   1.755  Ker3446 (N34)
     LUT2:I1->O            1   0.549   1.035  seg_data<7>43 (seg_data_7_OBUF)
     OBUF:I->O                 4.668          seg_data_7_OBUF (seg_data<7>)
    ----------------------------------------
    Total                     15.419ns (7.949ns logic, 7.470ns route)
                                       (51.6% logic, 48.4% route)

=========================================================================
CPU : 11.06 / 12.39 s | Elapsed : 11.00 / 12.00 s
 
--> 

Total memory usage is 76804 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    5 (   0 filtered)
Number of infos    :    0 (   0 filtered)