uart.syr

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

Release 7.1.04i - xst H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 1.14 s | Elapsed : 0.00 / 1.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 1.14 s | Elapsed : 0.00 / 1.00 s
 
--> Reading design: uart.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "uart.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "uart"
Output Format                      : NGC
Target Device                      : xc2s50-6-TQ144

---- Source Options
Top Module Name                    : uart
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : uart.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
tristate2logic                     : Yes
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3215 - Unit work/UART is now defined in a different file: was E:/temp/95144/vhdl/uart/UART.vhd, now is E:/temp/SPARTAN2/vhdl/Interface/uart/UART.vhd
WARNING:HDLParsers:3215 - Unit work/UART/ARCH is now defined in a different file: was E:/temp/95144/vhdl/uart/UART.vhd, now is E:/temp/SPARTAN2/vhdl/Interface/uart/UART.vhd
Compiling vhdl file "E:/temp/SPARTAN2/vhdl/Interface/uart/UART.vhd" in Library work.
Architecture arch of Entity uart is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <uart> (Architecture <arch>).
Entity <uart> analyzed. Unit <uart> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <uart>.
    Related source file is "E:/temp/SPARTAN2/vhdl/Interface/uart/UART.vhd".
    Found 1-bit 4-to-1 multiplexer for signal <$n0015>.
    Found 4-bit 4-to-1 multiplexer for signal <$n0024>.
    Found 20-bit adder for signal <$n0034> created at line 75.
    Found 4-bit adder for signal <$n0035> created at line 321.
    Found 3-bit comparator less for signal <$n0041> created at line 195.
    Found 1-bit 4-to-1 multiplexer for signal <$n0049>.
    Found 4-bit comparator greatequal for signal <$n0093> created at line 317.
    Found 4-bit comparator lessequal for signal <$n0094> created at line 317.
    Found 4-bit comparator less for signal <$n0096> created at line 317.
    Found 4-bit comparator greater for signal <$n0097> created at line 317.
    Found 1-bit register for signal <clkbaud8x>.
    Found 20-bit register for signal <cnt_delay>.
    Found 3-bit up counter for signal <div8_rec_reg>.
    Found 3-bit up counter for signal <div8_tras_reg>.
    Found 16-bit up counter for signal <div_reg>.
    Found 1-bit register for signal <key_entry1>.
    Found 1-bit register for signal <key_entry2>.
    Found 1-bit register for signal <recstart>.
    Found 1-bit register for signal <recstart_tmp>.
    Found 8-bit register for signal <rxd_buf>.
    Found 1-bit register for signal <rxd_reg1>.
    Found 1-bit register for signal <rxd_reg2>.
    Found 3-bit up counter for signal <send_state>.
    Found 1-bit register for signal <start_delaycnt>.
    Found 4-bit register for signal <state_rec>.
    Found 4-bit up counter for signal <state_tras>.
    Found 1-bit register for signal <trasstart>.
    Found 8-bit register for signal <txd_buf>.
    Found 1-bit register for signal <txd_reg>.
    Summary:
	inferred   5 Counter(s).
	inferred  50 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
	inferred   5 Comparator(s).
	inferred   6 Multiplexer(s).
Unit <uart> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 2
 20-bit adder                      : 1
 4-bit adder                       : 1
# Counters                         : 5
 16-bit up counter                 : 1
 3-bit up counter                  : 3
 4-bit up counter                  : 1
# Registers                        : 28
 1-bit register                    : 26
 20-bit register                   : 1
 4-bit register                    : 1
# Comparators                      : 5
 3-bit comparator less             : 1
 4-bit comparator greatequal       : 1
 4-bit comparator greater          : 1
 4-bit comparator less             : 1
 4-bit comparator lessequal        : 1
# Multiplexers                     : 3
 1-bit 4-to-1 multiplexer          : 2
 4-bit 4-to-1 multiplexer          : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1988 - Unit <uart>: instances <Mcompar__n0097>, <Mcompar__n0094> of unit <LPM_COMPARE_5> and unit <LPM_COMPARE_3> are dual, second instance is removed
WARNING:Xst:1988 - Unit <uart>: instances <Mcompar__n0096>, <Mcompar__n0093> of unit <LPM_COMPARE_4> and unit <LPM_COMPARE_2> are dual, second instance is removed

Optimizing unit <uart> ...
WARNING:Xst:1710 - FF/Latch  <txd_buf_7> (without init value) has a constant value of 0 in block <uart>.
Loading device for application Rf_Device from file 'v50.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block uart, actual ratio is 14.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : uart.ngr
Top Level Output File Name         : uart
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 21

Macro Statistics :
# Registers                        : 31
#      1-bit register              : 26
#      20-bit register             : 1
#      3-bit register              : 3
#      4-bit register              : 1
# Counters                         : 2
#      16-bit up counter           : 1
#      4-bit up counter            : 1
# Multiplexers                     : 3