uart.gyd

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

Pin Freeze File:  version H.42

95144XL144TQ XC95144XL-10-TQ144
clk S:PIN128
key_input S:PIN70
rst S:PIN71
rxd S:PIN77
seg_data<0> S:PIN119
en<6> S:PIN133
en<5> S:PIN125
en<4> S:PIN124
en<3> S:PIN120
en<2> S:PIN126
en<1> S:PIN131
en<0> S:PIN132
en<7> S:PIN134
seg_data<1> S:PIN118
seg_data<2> S:PIN116
seg_data<3> S:PIN115
seg_data<4> S:PIN113
seg_data<5> S:PIN111
seg_data<6> S:PIN107
seg_data<7> S:PIN106
txd S:PIN79


;The remaining section of the .gyd file is for documentation purposes only.
;It shows where your internal equations were placed in the last successful fit.

PARTITION FB1_1 start_delaycnt key_entry1 cnt_delay<9> cnt_delay<7>
		 cnt_delay<6> cnt_delay<5> cnt_delay<17> cnt_delay<16>
		 cnt_delay<15> cnt_delay<14> cnt_delay<11> cnt_delay<0>
		 cnt_delay<8> cnt_delay<19> cnt_delay<18> cnt_delay<13>
		 cnt_delay<12> cnt_delay<10>
PARTITION FB2_1 EXP10_ txd_buf<4> state_tras<1> send_state<0>
		 div8_tras_reg<0> send_state<2> state_tras<3> txd_buf<5>
		 EXP11_ send_state<1> key_entry2 state_tras<2>
		 div8_tras_reg<2> div8_tras_reg<1> EXP12_ state_tras<0>
		 EXP13_ txd_buf<6>
PARTITION FB3_12 div_reg<0> div_reg<1> div8_rec_reg<0> cnt_delay<4>
		 cnt_delay<3> cnt_delay<2> cnt_delay<1>
PARTITION FB4_1 seg_data_1_OBUF en_6_OBUF$BUF4 en_6_OBUF$BUF0 EXP14_
		 rxd_buf<6> EXP15_ rxd_buf<5> rxd_buf<4>
		 en_6_OBUF$BUF5 rxd_buf<3> en_6_OBUF$BUF6 en_7_OBUF
		 EXP16_ rxd_buf<1> EXP17_ rxd_buf<0>
		 EXP18_ rxd_buf<2>

PARTITION FB6_1 state_rec<2> seg_data_7_OBUF state_rec<1> seg_data_5_OBUF
		 state_rec<3> recstart_tmp recstart seg_data_4_OBUF
		 seg_data_2_OBUF seg_data_3_OBUF en_6_OBUF en_6_OBUF$BUF3
		 div8_rec_reg<2> div8_rec_reg<1> en_6_OBUF$BUF2 state_rec<0>
		 en_6_OBUF$BUF1 rxd_buf<7>
PARTITION FB7_1 EXP19_ EXP20_ EXP21_ txd_buf<1>
		 EXP22_ EXP23_ txd_buf<3> EXP24_
		 EXP25_ txd_reg EXP26_ EXP27_
		 txd_buf<2> EXP28_ txd_buf<0> EXP29_
		 EXP30_ trasstart
PARTITION FB8_1 rxd_reg2 rxd_reg1 div_reg<9> div_reg<7>
		 div_reg<6> div_reg<5> div_reg<4> div_reg<3>
		 div_reg<15> div_reg<14> div_reg<13> div_reg<12>
		 div_reg<11> div_reg<10> clkbaud8x seg_data_6_OBUF
		 div_reg<8> div_reg<2>