mcu.syr

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

Release 7.1.04i - xst H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
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--> Reading design: mcu.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "mcu.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "mcu"
Output Format                      : NGC
Target Device                      : xc2s50-6-tq144

---- Source Options
Top Module Name                    : mcu
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : mcu.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
tristate2logic                     : Yes
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "E:/temp/SPARTAN2/vhdl/Interface/MCU/MCU.vhd" in Library work.
Architecture arch of Entity mcu is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <mcu> (Architecture <arch>).
    Set property "clock_buffer = ibuf" for signal <mcu_ale> in unit <mcu>.
    Set property "clock_buffer = ibuf" for signal <mcu_nwr> in unit <mcu>.
WARNING:Xst:819 - "E:/temp/SPARTAN2/vhdl/Interface/MCU/MCU.vhd" line 53: The following signals are missing in the process sensitivity list:
   DIN<1>, DIN<0>.
Entity <mcu> analyzed. Unit <mcu> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <mcu>.
    Related source file is "E:/temp/SPARTAN2/vhdl/Interface/MCU/MCU.vhd".
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:1780 - Signal <state> is never used or assigned.
WARNING:Xst:737 - Found 2-bit latch for signal <LA>.
    Found 8-bit tristate buffer for signal <data>.
    Found 8-bit register for signal <REG2>.
    Summary:
	inferred   8 D-type flip-flop(s).
	inferred   8 Tristate(s).
Unit <mcu> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 1
 8-bit register                    : 1
# Latches                          : 1
 2-bit latch                       : 1
# Tristates                        : 1
 8-bit tristate buffer             : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <mcu> ...
Loading device for application Rf_Device from file 'v50.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block mcu, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : mcu.ngr
Top Level Output File Name         : mcu
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 29

Macro Statistics :
# Registers                        : 1
#      8-bit register              : 1
# Tristates                        : 1
#      8-bit tristate buffer       : 1

Cell Usage :
# BELS                             : 11
#      INV                         : 1
#      LUT2                        : 2
#      LUT3                        : 8
# FlipFlops/Latches                : 10
#      FDCE_1                      : 8
#      LD                          : 2
# IO Buffers                       : 28
#      IBUF                        : 12
#      IOBUF                       : 8
#      OBUF                        : 8
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-6 

 Number of Slices:                       6  out of    768     0%  
 Number of Slice Flip Flops:            10  out of   1536     0%  
 Number of 4 input LUTs:                10  out of   1536     0%  
 Number of bonded IOBs:                 29  out of     96    30%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
mcu_nwr                            | IBUF                   | 8     |
mcu_ale                            | IBUF                   | 2     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: No path found
   Minimum input arrival time before clock: 2.691ns
   Maximum output required time after clock: 9.354ns
   Maximum combinational path delay: 9.309ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'mcu_nwr'
  Total number of paths / destination ports: 8 / 8
-------------------------------------------------------------------------
Offset:              2.691ns (Levels of Logic = 1)
  Source:            data<0> (PAD)
  Destination:       REG2_0 (FF)
  Destination Clock: mcu_nwr falling

  Data Path: data<0> to REG2_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IOBUF:IO->O           2   0.776   1.206  data_0_IOBUF (N0)
     FDCE_1:D                  0.709          REG2_0
    ----------------------------------------
    Total                      2.691ns (1.485ns logic, 1.206ns route)
                                       (55.2% logic, 44.8% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'mcu_ale'
  Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Offset:              2.691ns (Levels of Logic = 1)
  Source:            data<0> (PAD)
  Destination:       LA_0 (LATCH)
  Destination Clock: mcu_ale falling

  Data Path: data<0> to LA_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IOBUF:IO->O           2   0.776   1.206  data_0_IOBUF (N0)
     LD:D                      0.709          LA_0
    ----------------------------------------
    Total                      2.691ns (1.485ns logic, 1.206ns route)
                                       (55.2% logic, 44.8% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'mcu_ale'
  Total number of paths / destination ports: 16 / 8
-------------------------------------------------------------------------
Offset:              9.354ns (Levels of Logic = 2)
  Source:            LA_0 (LATCH)
  Destination:       data<0> (PAD)
  Source Clock:      mcu_ale falling

  Data Path: LA_0 to data<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               9   1.194   1.908  LA_0 (LA_0)
     LUT3:I0->O            1   0.549   1.035  DOUT<5>1 (DOUT<5>)
     IOBUF:I->IO               4.668          data_5_IOBUF (data<5>)
    ----------------------------------------
    Total                      9.354ns (6.411ns logic, 2.943ns route)
                                       (68.5% logic, 31.5% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'mcu_nwr'
  Total number of paths / destination ports: 8 / 8
-------------------------------------------------------------------------
Offset:              6.788ns (Levels of Logic = 1)
  Source:            REG2_7 (FF)
  Destination:       ledout<7> (PAD)
  Source Clock:      mcu_nwr falling

  Data Path: REG2_7 to ledout<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE_1:C->Q           1   1.085   1.035  REG2_7 (REG2_7)
     OBUF:I->O                 4.668          ledout_7_OBUF (ledout<7>)
    ----------------------------------------
    Total                      6.788ns (5.753ns logic, 1.035ns route)
                                       (84.8% logic, 15.2% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 24 / 8
-------------------------------------------------------------------------
Delay:               9.309ns (Levels of Logic = 3)
  Source:            mcu_ale (PAD)
  Destination:       data<0> (PAD)

  Data Path: mcu_ale to data<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             3   0.776   1.332  mcu_ale_IBUF (mcu_ale_IBUF)
     LUT2:I0->O            8   0.549   1.845  data_DOUT_EnableTr_INV1 (data_DOUT_N0)
     IOBUF:T->IO               4.807          data_6_IOBUF (data<6>)
    ----------------------------------------
    Total                      9.309ns (6.132ns logic, 3.177ns route)
                                       (65.9% logic, 34.1% route)

=========================================================================
CPU : 7.20 / 7.91 s | Elapsed : 7.00 / 8.00 s
 
--> 

Total memory usage is 75780 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    4 (   0 filtered)
Number of infos    :    0 (   0 filtered)