mcu.vhd

来自「Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档」· VHDL 代码 · 共 90 行

--作为单片机和CPLD的简单示例，演示如何采用地址数据总线方式和CPLD通讯
--单片机读取拨码开关值，并将其开关状态用写入cpld
--cpld的led显示

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY MCU IS

   PORT (
   
      rst                     : IN std_logic;
      clk                     : IN std_logic;
       
--********单片机接口信号********--
      data                    : INOUT std_logic_vector(7 DOWNTO 0);   --数据地址总线，
                                                                    --即单片机的P0端口  
      mcu_ale                 : IN  std_logic;    -- mcu的ALE 地址锁存信号
      mcu_nrd                 : IN  std_logic;    -- mcu的rd
      mcu_nwr                 : IN  std_logic;    -- mcu的wr
--*******外围控制器件接口*******--
      dial                    : IN  std_logic_vector(7 downto 0);
      ledout                  : OUT std_logic_vector(7 downto 0)

  --    EN                      : buffer std_logic_vector(1 downto 0);
  --    segdata                 : OUT std_logic_vector(7 downto 0)

      );  
END MCU;


ARCHITECTURE arch OF MCU IS

attribute	clock_buffer  : string;
attribute   clock_buffer  of	 mcu_ale :signal is "ibuf";				  
attribute   clock_buffer  of   mcu_nwr  :signal is "ibuf";

SIGNAL LA: std_logic_vector(1 DOWNTO 0); --低位地址锁存信号
SIGNAL state : std_logic_vector(4 DOWNTO 0);
SIGNAL DIN : std_logic_vector(7 DOWNTO 0);--总线输入
SIGNAL DOUT : std_logic_vector(7 DOWNTO 0);--总线输出
SIGNAL REG2 : std_logic_vector(7 DOWNTO 0);--led灯状态寄存器



BEGIN




process(mcu_ale)
begin
 
  if(mcu_ale='1')THEN
  LA<=DIN(1 DOWNTO 0);
  END IF;
END PROCESS;


ledout <=reg2;

DOUT<= dial WHEN LA ="00" ELSE                   
       "11111111";
DIN    <= DATA;
DATA   <= DOUT WHEN mcu_nrd ='0' AND mcu_ale='0' ELSE "ZZZZZZZZ";

READ :PROCESS(mcu_nwr,rst)

      BEGIN 
            IF rst='0' THEN
            REG2<="00000000";        
            
            ELSIF mcu_nwr'EVENT AND mcu_nwr='0' THEN 
            CASE LA IS  --- Address input
              WHEN "10"=>
                REG2 <= DIN;   
              WHEN OTHERS =>
            END CASE;
            END IF;
      END PROCESS READ;





END arch;