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📄 dial1.rpt

📁 Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档
💻 RPT
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en<2>                 0       0   /\3   2     FB4_2   126   I/O     O
en<6>                 0       0     0   5     FB4_3   133   I/O     O
(unused)              0       0     0   5     FB4_4         (b)     
(unused)              0       0     0   5     FB4_5   128   I/O     I
(unused)              0       0     0   5     FB4_6   129   I/O     
(unused)              0       0     0   5     FB4_7         (b)     
(unused)              0       0     0   5     FB4_8   130   I/O     
en<0>                 2       0     0   3     FB4_9   131   I/O     O
(unused)              0       0     0   5     FB4_10  135   I/O     
en<1>                 2       0     0   3     FB4_11  132   I/O     O
en<7>                 0       0     0   5     FB4_12  134   I/O     O
(unused)              0       0     0   5     FB4_13  137   I/O     
(unused)              0       0     0   5     FB4_14  136   I/O     
(unused)              0       0     0   5     FB4_15  138   I/O     
(unused)              0       0     0   5     FB4_16  139   I/O     
cnt_scan<4>           3       0     0   2     FB4_17  140   I/O     (b)
cnt_scan<3>           3       0   \/1   1     FB4_18        (b)     (b)

Signals Used by Logic in Function Block
  1: clk                7: datain<0>         13: datain<6> 
  2: cnt_scan<0>        8: datain<1>         14: datain<7> 
  3: cnt_scan<15>       9: datain<2>         15: en<0> 
  4: cnt_scan<1>       10: datain<3>         16: en<1> 
  5: cnt_scan<2>       11: datain<4>         17: rst 
  6: cnt_scan<3>       12: datain<5>        

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
dataout<1>           ......XXXXXXXXXX........................ 10
en<2>                ........................................ 0
en<6>                ........................................ 0
en<0>                ..X.............X....................... 2
en<1>                ..X.............X....................... 2
en<7>                ........................................ 0
cnt_scan<4>          XX.XXX..........X....................... 6
cnt_scan<3>          XX.XX...........X....................... 5
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB5  ***********************************
Number of function block inputs used/remaining:               0/54
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB5_1         (b)     
(unused)              0       0     0   5     FB5_2   52    I/O     
(unused)              0       0     0   5     FB5_3   59    I/O     I
(unused)              0       0     0   5     FB5_4         (b)     
(unused)              0       0     0   5     FB5_5   53    I/O     
(unused)              0       0     0   5     FB5_6   54    I/O     
(unused)              0       0     0   5     FB5_7   66    I/O     I
(unused)              0       0     0   5     FB5_8   56    I/O     I
(unused)              0       0     0   5     FB5_9   57    I/O     I
(unused)              0       0     0   5     FB5_10  68    I/O     
(unused)              0       0     0   5     FB5_11  58    I/O     I
(unused)              0       0     0   5     FB5_12  60    I/O     
(unused)              0       0     0   5     FB5_13  70    I/O     
(unused)              0       0     0   5     FB5_14  61    I/O     I
(unused)              0       0     0   5     FB5_15  64    I/O     I
(unused)              0       0     0   5     FB5_16        (b)     
(unused)              0       0     0   5     FB5_17  69    I/O     I
(unused)              0       0     0   5     FB5_18        (b)     
*********************************** FB6  ***********************************
Number of function block inputs used/remaining:               17/37
Number of signals used by logic mapping into function block:  17
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
dataout<2>_BUFR      12       7<-   0   0     FB6_1         (b)     (b)
dataout<7>            1       0   /\2   2     FB6_2   106   I/O     O
(unused)              0       0   \/3   2     FB6_3         (b)     (b)
dataout<5>            9       4<-   0   0     FB6_4   111   I/O     O
cnt_scan<0>           2       0   /\1   2     FB6_5   110   I/O     (b)
cnt_scan<2>           3       0     0   2     FB6_6   112   I/O     (b)
cnt_scan<1>           3       0     0   2     FB6_7         (b)     (b)
dataout<4>            1       0     0   4     FB6_8   113   I/O     O
dataout<2>            1       0   \/2   2     FB6_9   116   I/O     O
dataout<3>            9       4<-   0   0     FB6_10  115   I/O     O
dataout<0>            0       0   /\2   3     FB6_11  119   I/O     O
en<3>                 0       0   \/2   3     FB6_12  120   I/O     O
dataout<7>_BUFR      12       7<-   0   0     FB6_13        (b)     (b)
(unused)              0       0   /\5   0     FB6_14  121   I/O     (b)
en<4>                 0       0   \/4   1     FB6_15  124   I/O     O
dataout<4>_BUFR      12       7<-   0   0     FB6_16  117   I/O     (b)
en<5>                 0       0   /\3   2     FB6_17  125   I/O     O
(unused)              0       0   \/5   0     FB6_18        (b)     (b)

Signals Used by Logic in Function Block
  1: clk                7: datain<3>         13: dataout<4>_BUFR 
  2: cnt_scan<0>        8: datain<4>         14: dataout<7>_BUFR 
  3: cnt_scan<1>        9: datain<5>         15: en<0> 
  4: datain<0>         10: datain<6>         16: en<1> 
  5: datain<1>         11: datain<7>         17: rst 
  6: datain<2>         12: dataout<2>_BUFR  

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
dataout<2>_BUFR      ...XXXXXXXX...XX........................ 10
dataout<7>           .............X.......................... 1
dataout<5>           ...XXXXXXXX...XX........................ 10
cnt_scan<0>          X...............X....................... 2
cnt_scan<2>          XXX.............X....................... 4
cnt_scan<1>          XX..............X....................... 3
dataout<4>           ............X........................... 1
dataout<2>           ...........X............................ 1
dataout<3>           ...XXXXXXXX...XX........................ 10
dataout<0>           ........................................ 0
en<3>                ........................................ 0
dataout<7>_BUFR      ...XXXXXXXX...XX........................ 10
en<4>                ........................................ 0
dataout<4>_BUFR      ...XXXXXXXX...XX........................ 10
en<5>                ........................................ 0
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB7  ***********************************
Number of function block inputs used/remaining:               0/54
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB7_1         (b)     
(unused)              0       0     0   5     FB7_2   71    I/O     I
(unused)              0       0     0   5     FB7_3   75    I/O     
(unused)              0       0     0   5     FB7_4         (b)     
(unused)              0       0     0   5     FB7_5   74    I/O     
(unused)              0       0     0   5     FB7_6   76    I/O     
(unused)              0       0     0   5     FB7_7   77    I/O     
(unused)              0       0     0   5     FB7_8   78    I/O     
(unused)              0       0     0   5     FB7_9   80    I/O     
(unused)              0       0     0   5     FB7_10  79    I/O     
(unused)              0       0     0   5     FB7_11  82    I/O     
(unused)              0       0     0   5     FB7_12  85    I/O     
(unused)              0       0     0   5     FB7_13  81    I/O     
(unused)              0       0     0   5     FB7_14  86    I/O     
(unused)              0       0     0   5     FB7_15  87    I/O     
(unused)              0       0     0   5     FB7_16  83    I/O     
(unused)              0       0     0   5     FB7_17  88    I/O     
(unused)              0       0     0   5     FB7_18        (b)     
*********************************** FB8  ***********************************
Number of function block inputs used/remaining:               17/37
Number of signals used by logic mapping into function block:  17
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB8_1         (b)     
(unused)              0       0     0   5     FB8_2   91    I/O     
(unused)              0       0     0   5     FB8_3   95    I/O     
(unused)              0       0     0   5     FB8_4   97    I/O     
(unused)              0       0     0   5     FB8_5   92    I/O     
(unused)              0       0     0   5     FB8_6   93    I/O     
(unused)              0       0     0   5     FB8_7         (b)     
(unused)              0       0     0   5     FB8_8   94    I/O     
(unused)              0       0     0   5     FB8_9   96    I/O     
(unused)              0       0     0   5     FB8_10  101   I/O     
(unused)              0       0     0   5     FB8_11  98    I/O     
(unused)              0       0     0   5     FB8_12  100   I/O     
(unused)              0       0     0   5     FB8_13  103   I/O     
(unused)              0       0     0   5     FB8_14  102   I/O     
(unused)              0       0   \/4   1     FB8_15  104   I/O     (b)
dataout<6>           12       7<-   0   0     FB8_16  107   I/O     O
(unused)              0       0   /\3   2     FB8_17  105   I/O     (b)
cnt_scan<5>           3       0     0   2     FB8_18        (b)     (b)

Signals Used by Logic in Function Block
  1: clk                7: datain<0>         13: datain<6> 
  2: cnt_scan<0>        8: datain<1>         14: datain<7> 
  3: cnt_scan<1>        9: datain<2>         15: en<0> 
  4: cnt_scan<2>       10: datain<3>         16: en<1> 
  5: cnt_scan<3>       11: datain<4>         17: rst 
  6: cnt_scan<4>       12: datain<5>        

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
dataout<6>           ......XXXXXXXXXX........................ 10
cnt_scan<5>          XXXXXX..........X....................... 7
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********











FTCPE_cnt_scan0: FTCPE port map (cnt_scan(0),'1',clk,NOT rst,'0');

FTCPE_cnt_scan1: FTCPE port map (cnt_scan(1),cnt_scan(0),clk,NOT rst,'0');

FTCPE_cnt_scan2: FTCPE port map (cnt_scan(2),cnt_scan_T(2),clk,NOT rst,'0');
cnt_scan_T(2) <= (cnt_scan(0) AND cnt_scan(1));

FTCPE_cnt_scan3: FTCPE port map (cnt_scan(3),cnt_scan_T(3),clk,NOT rst,'0');
cnt_scan_T(3) <= (cnt_scan(0) AND cnt_scan(1) AND cnt_scan(2));

FTCPE_cnt_scan4: FTCPE port map (cnt_scan(4),cnt_scan_T(4),clk,NOT rst,'0');
cnt_scan_T(4) <= (cnt_scan(0) AND cnt_scan(1) AND cnt_scan(2) AND 
	cnt_scan(3));

FTCPE_cnt_scan5: FTCPE port map (cnt_scan(5),cnt_scan_T(5),clk,NOT rst,'0');
cnt_scan_T(5) <= (cnt_scan(0) AND cnt_scan(1) AND cnt_scan(2) AND 
	cnt_scan(3) AND cnt_scan(4));

FTCPE_cnt_scan6: FTCPE port map (cnt_scan(6),cnt_scan_T(6),clk,NOT rst,'0');
cnt_scan_T(6) <= (cnt_scan(0) AND cnt_scan(1) AND cnt_scan(2) AND 
	cnt_scan(3) AND cnt_scan(4) AND cnt_scan(5));

FTCPE_cnt_scan7: FTCPE port map (cnt_scan(7),cnt_scan_T(7),clk,NOT rst,'0');
cnt_scan_T(7) <= (cnt_scan(0) AND cnt_scan(1) AND cnt_scan(2) AND 
	cnt_scan(3) AND cnt_scan(4) AND cnt_scan(5) AND cnt_scan(6));

FTCPE_cnt_scan8: FTCPE port map (cnt_scan(8),cnt_scan_T(8),clk,NOT rst,'0');
cnt_scan_T(8) <= (cnt_scan(0) AND cnt_scan(1) AND cnt_scan(2) AND 
	cnt_scan(3) AND cnt_scan(4) AND cnt_scan(5) AND cnt_scan(6) AND 
	cnt_scan(7));

FTCPE_cnt_scan9: FTCPE port map (cnt_scan(9),cnt_scan_T(9),clk,NOT rst,'0');
cnt_scan_T(9) <= (cnt_scan(0) AND cnt_scan(1) AND cnt_scan(2) AND 
	cnt_scan(3) AND cnt_scan(4) AND cnt_scan(5) AND cnt_scan(6) AND 
	cnt_scan(7) AND cnt_scan(8));

FTCPE_cnt_scan10: FTCPE port map (cnt_scan(10),cnt_scan_T(10),clk,NOT rst,'0');
cnt_scan_T(10) <= (cnt_scan(0) AND cnt_scan(1) AND cnt_scan(2) AND 
	cnt_scan(3) AND cnt_scan(4) AND cnt_scan(5) AND cnt_scan(6) AND 
	cnt_scan(7) AND cnt_scan(8) AND cnt_scan(9));

FTCPE_cnt_scan11: FTCPE port map (cnt_scan(11),cnt_scan_T(11),clk,NOT rst,'0');
cnt_scan_T(11) <= (cnt_scan(0) AND cnt_scan(10) AND cnt_scan(1) AND 
	cnt_scan(2) AND cnt_scan(3) AND cnt_scan(4) AND cnt_scan(5) AND 
	cnt_scan(6) AND cnt_scan(7) AND cnt_scan(8) AND cnt_scan(9));

FTCPE_cnt_scan12: FTCPE port map (cnt_scan(12),cnt_scan_T(12),clk,NOT rst,'0');
cnt_scan_T(12) <= (cnt_scan(0) AND cnt_scan(10) AND cnt_scan(11) AND 
	cnt_scan(1) AND cnt_scan(2) AND cnt_scan(3) AND cnt_scan(4) AND 
	cnt_scan(5) AND cnt_scan(6) AND cnt_scan(7) AND cnt_scan(8) AND 
	cnt_scan(9));

FTCPE_cnt_scan13: FTCPE port map (cnt_scan(13),cnt_scan_T(13),clk,NOT rst,'0');
cnt_scan_T(13) <= (cnt_scan(0) AND cnt_scan(10) AND cnt_scan(11) AND 
	cnt_scan(12) AND cnt_scan(1) AND cnt_scan(2) AND cnt_scan(3) AND 
	cnt_scan(4) AND cnt_scan(5) AND cnt_scan(6) AND cnt_scan(7) AND 

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