dial1.syr

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

#      16-bit adder                : 1

Cell Usage :
# BELS                             : 62
#      GND                         : 1
#      INV                         : 4
#      LUT1_L                      : 15
#      LUT4                        : 11
#      MUXCY                       : 15
#      VCC                         : 1
#      XORCY                       : 15
# FlipFlops/Latches                : 18
#      FDC                         : 17
#      FDP                         : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 25
#      IBUF                        : 9
#      OBUF                        : 16
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-5 

 Number of Slices:                      15  out of    768     1%  
 Number of Slice Flip Flops:            18  out of   1536     1%  
 Number of 4 input LUTs:                26  out of   1536     1%  
 Number of bonded IOBs:                 26  out of     96    27%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
cnt_scan_15:Q                      | NONE                   | 2     |
clk                                | BUFGP                  | 16    |
-----------------------------------+------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 5.832ns (Maximum Frequency: 171.468MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 13.105ns
   Maximum combinational path delay: 12.037ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'cnt_scan_15:Q'
  Clock period: 5.698ns (frequency: 175.500MHz)
  Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Delay:               5.698ns (Levels of Logic = 1)
  Source:            en_xhdl_0 (FF)
  Destination:       en_xhdl_0 (FF)
  Source Clock:      cnt_scan_15:Q rising
  Destination Clock: cnt_scan_15:Q rising

  Data Path: en_xhdl_0 to en_xhdl_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              6   1.292   1.850  en_xhdl_0 (en_xhdl_0)
     INV:I->O              1   0.653   1.150  _n00041_INV_0 (_n0004)
     FDC:D                     0.753          en_xhdl_0
    ----------------------------------------
    Total                      5.698ns (2.698ns logic, 3.000ns route)
                                       (47.3% logic, 52.7% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 5.832ns (frequency: 171.468MHz)
  Total number of paths / destination ports: 136 / 16
-------------------------------------------------------------------------
Delay:               5.832ns (Levels of Logic = 17)
  Source:            cnt_scan_0 (FF)
  Destination:       cnt_scan_15 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: cnt_scan_0 to cnt_scan_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              1   1.292   1.150  cnt_scan_0 (cnt_scan_0)
     INV:I->O              2   0.653   0.000  dial1_cnt_scan__n0000<0>lut_INV_0 (N3)
     MUXCY:S->O            1   0.784   0.000  dial1_cnt_scan__n0000<0>cy (dial1_cnt_scan__n0000<0>_cyo)
     MUXCY:CI->O           1   0.050   0.000  dial1_cnt_scan__n0000<1>cy (dial1_cnt_scan__n0000<1>_cyo)
     MUXCY:CI->O           1   0.050   0.000  dial1_cnt_scan__n0000<2>cy (dial1_cnt_scan__n0000<2>_cyo)
     MUXCY:CI->O           1   0.050   0.000  dial1_cnt_scan__n0000<3>cy (dial1_cnt_scan__n0000<3>_cyo)
     MUXCY:CI->O           1   0.050   0.000  dial1_cnt_scan__n0000<4>cy (dial1_cnt_scan__n0000<4>_cyo)
     MUXCY:CI->O           1   0.050   0.000  dial1_cnt_scan__n0000<5>cy (dial1_cnt_scan__n0000<5>_cyo)
     MUXCY:CI->O           1   0.050   0.000  dial1_cnt_scan__n0000<6>cy (dial1_cnt_scan__n0000<6>_cyo)
     MUXCY:CI->O           1   0.050   0.000  dial1_cnt_scan__n0000<7>cy (dial1_cnt_scan__n0000<7>_cyo)
     MUXCY:CI->O           1   0.050   0.000  dial1_cnt_scan__n0000<8>cy (dial1_cnt_scan__n0000<8>_cyo)
     MUXCY:CI->O           1   0.050   0.000  dial1_cnt_scan__n0000<9>cy (dial1_cnt_scan__n0000<9>_cyo)
     MUXCY:CI->O           1   0.050   0.000  dial1_cnt_scan__n0000<10>cy (dial1_cnt_scan__n0000<10>_cyo)
     MUXCY:CI->O           1   0.050   0.000  dial1_cnt_scan__n0000<11>cy (dial1_cnt_scan__n0000<11>_cyo)
     MUXCY:CI->O           1   0.050   0.000  dial1_cnt_scan__n0000<12>cy (dial1_cnt_scan__n0000<12>_cyo)
     MUXCY:CI->O           1   0.050   0.000  dial1_cnt_scan__n0000<13>cy (dial1_cnt_scan__n0000<13>_cyo)
     MUXCY:CI->O           0   0.050   0.000  dial1_cnt_scan__n0000<14>cy (dial1_cnt_scan__n0000<14>_cyo)
     XORCY:CI->O           1   0.500   0.000  dial1_cnt_scan__n0000<15>_xor (cnt_scan__n0000<15>)
     FDC:D                     0.753          cnt_scan_15
    ----------------------------------------
    Total                      5.832ns (4.682ns logic, 1.150ns route)
                                       (80.3% logic, 19.7% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'cnt_scan_15:Q'
  Total number of paths / destination ports: 58 / 9
-------------------------------------------------------------------------
Offset:              13.105ns (Levels of Logic = 3)
  Source:            en_xhdl_0 (FF)
  Destination:       dataout<7> (PAD)
  Source Clock:      cnt_scan_15:Q rising

  Data Path: en_xhdl_0 to dataout<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              6   1.292   1.850  en_xhdl_0 (en_xhdl_0)
     LUT4:I1->O            7   0.653   1.950  data4<0>1 (data4<0>)
     LUT4:I0->O            1   0.653   1.150  Mrom_dataout_xhdl1_inst_lut4_71 (dataout_7_OBUF)
     OBUF:I->O                 5.557          dataout_7_OBUF (dataout<7>)
    ----------------------------------------
    Total                     13.105ns (8.155ns logic, 4.950ns route)
                                       (62.2% logic, 37.8% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 56 / 7
-------------------------------------------------------------------------
Delay:               12.037ns (Levels of Logic = 4)
  Source:            datain<0> (PAD)
  Destination:       dataout<7> (PAD)

  Data Path: datain<0> to dataout<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.924   1.150  datain_0_IBUF (datain_0_IBUF)
     LUT4:I0->O            7   0.653   1.950  data4<0>1 (data4<0>)
     LUT4:I0->O            1   0.653   1.150  Mrom_dataout_xhdl1_inst_lut4_71 (dataout_7_OBUF)
     OBUF:I->O                 5.557          dataout_7_OBUF (dataout<7>)
    ----------------------------------------
    Total                     12.037ns (7.787ns logic, 4.250ns route)
                                       (64.7% logic, 35.3% route)

=========================================================================
CPU : 4.20 / 4.61 s | Elapsed : 4.00 / 4.00 s
 
--> 

Total memory usage is 74756 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    2 (   0 filtered)