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📄 lcd1.rpt

📁 Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档
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Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
data<6>              .XX..X.X..XXXXXX........................ 10
lcd_e                .......XX.XXXXXX........................ 8
data<5>_BUFR         .X..X..X..XXXXXX........................ 9
lcd_rw               ........................................ 0
state_FFd1           .......X..XXXXXX........................ 7
lcd_rs               .......X.XXXXXXX........................ 8
state_FFd3           .......X..X...XX........................ 4
div_cnt<0>           X.........X............................. 2
data<7>_BUFR         .XXX..XX..XXXXXX........................ 11
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB5  ***********************************
Number of function block inputs used/remaining:               0/54
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB5_1         (b)     
(unused)              0       0     0   5     FB5_2   52    I/O     
(unused)              0       0     0   5     FB5_3   59    I/O     
(unused)              0       0     0   5     FB5_4         (b)     
(unused)              0       0     0   5     FB5_5   53    I/O     
(unused)              0       0     0   5     FB5_6   54    I/O     
(unused)              0       0     0   5     FB5_7   66    I/O     
(unused)              0       0     0   5     FB5_8   56    I/O     
(unused)              0       0     0   5     FB5_9   57    I/O     
(unused)              0       0     0   5     FB5_10  68    I/O     
(unused)              0       0     0   5     FB5_11  58    I/O     
(unused)              0       0     0   5     FB5_12  60    I/O     
(unused)              0       0     0   5     FB5_13  70    I/O     
(unused)              0       0     0   5     FB5_14  61    I/O     
(unused)              0       0     0   5     FB5_15  64    I/O     
(unused)              0       0     0   5     FB5_16        (b)     
(unused)              0       0     0   5     FB5_17  69    I/O     
(unused)              0       0     0   5     FB5_18        (b)     
*********************************** FB6  ***********************************
Number of function block inputs used/remaining:               21/33
Number of signals used by logic mapping into function block:  21
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0   \/5   0     FB6_1         (b)     (b)
data<0>              11       6<-   0   0     FB6_2   106   I/O     O
(unused)              0       0   \/1   4     FB6_3         (b)     (b)
data<2>              11       6<-   0   0     FB6_4   111   I/O     O
(unused)              0       0   /\5   0     FB6_5   110   I/O     (b)
(unused)              0       0   \/1   4     FB6_6   112   I/O     (b)
(unused)              0       0   \/5   0     FB6_7         (b)     (b)
data<3>              11       6<-   0   0     FB6_8   113   I/O     O
data<5>               1       0   \/2   2     FB6_9   116   I/O     O
data<4>              11       6<-   0   0     FB6_10  115   I/O     O
data<7>               1       0   /\4   0     FB6_11  119   I/O     O
lcd_psb               0       0     0   5     FB6_12  120   I/O     O
(unused)              0       0     0   5     FB6_13        (b)     
(unused)              0       0     0   5     FB6_14  121   I/O     
(unused)              0       0     0   5     FB6_15  124   I/O     
(unused)              0       0     0   5     FB6_16  117   I/O     
lcd_RSTB              3       0     0   2     FB6_17  125   I/O     O
(unused)              0       0   \/1   4     FB6_18        (b)     (b)

Signals Used by Logic in Function Block
  1: cnt<0>             8: cnt<7>            15: div_cnt<14> 
  2: cnt<1>             9: data<0>           16: nRST 
  3: cnt<2>            10: data<2>           17: state_FFd1 
  4: cnt<3>            11: data<3>           18: state_FFd2 
  5: cnt<4>            12: data<4>           19: state_FFd3 
  6: cnt<5>            13: data<5>_BUFR      20: state_FFd4 
  7: cnt<6>            14: data<7>_BUFR      21: state_FFd5 

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
data<0>              X.......X.....XXXXXXX................... 9
data<2>              ..X......X....XXXXXXX................... 9
data<3>              ...X......X...XXXXXXX................... 9
data<5>              ............X........................... 1
data<4>              ....X......X..XXXXXXX................... 9
data<7>              .............X.......................... 1
lcd_psb              ........................................ 0
lcd_RSTB             XXXXXXXX......XXXXXXX................... 15
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB7  ***********************************
Number of function block inputs used/remaining:               0/54
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB7_1         (b)     
(unused)              0       0     0   5     FB7_2   71    I/O     I
(unused)              0       0     0   5     FB7_3   75    I/O     
(unused)              0       0     0   5     FB7_4         (b)     
(unused)              0       0     0   5     FB7_5   74    I/O     
(unused)              0       0     0   5     FB7_6   76    I/O     
(unused)              0       0     0   5     FB7_7   77    I/O     
(unused)              0       0     0   5     FB7_8   78    I/O     
(unused)              0       0     0   5     FB7_9   80    I/O     
(unused)              0       0     0   5     FB7_10  79    I/O     
(unused)              0       0     0   5     FB7_11  82    I/O     
(unused)              0       0     0   5     FB7_12  85    I/O     
(unused)              0       0     0   5     FB7_13  81    I/O     
(unused)              0       0     0   5     FB7_14  86    I/O     
(unused)              0       0     0   5     FB7_15  87    I/O     
(unused)              0       0     0   5     FB7_16  83    I/O     
(unused)              0       0     0   5     FB7_17  88    I/O     
(unused)              0       0     0   5     FB7_18        (b)     
*********************************** FB8  ***********************************
Number of function block inputs used/remaining:               16/38
Number of signals used by logic mapping into function block:  16
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
state_FFd5            8       3<-   0   0     FB8_1         (b)     (b)
(unused)              0       0   \/5   0     FB8_2   91    I/O     (b)
state_FFd2            8       5<- \/2   0     FB8_3   95    I/O     (b)
(unused)              0       0   \/5   0     FB8_4   97    I/O     (b)
cnt<5>                9       7<- \/3   0     FB8_5   92    I/O     (b)
(unused)              0       0   \/5   0     FB8_6   93    I/O     (b)
cnt<4>               11       8<- \/2   0     FB8_7         (b)     (b)
(unused)              0       0   \/5   0     FB8_8   94    I/O     (b)
cnt<1>               11       7<- \/1   0     FB8_9   96    I/O     (b)
cnt<0>               11       6<-   0   0     FB8_10  101   I/O     (b)
(unused)              0       0   /\5   0     FB8_11  98    I/O     (b)
(unused)              0       0   \/5   0     FB8_12  100   I/O     (b)
(unused)              0       0   \/5   0     FB8_13  103   I/O     (b)
cnt<2>               12      10<- \/3   0     FB8_14  102   I/O     (b)
(unused)              0       0   \/5   0     FB8_15  104   I/O     (b)
data<1>              11       8<- \/2   0     FB8_16  107   I/O     O
cnt<6>                7       2<-   0   0     FB8_17  105   I/O     (b)
(unused)              0       0   \/3   2     FB8_18        (b)     (b)

Signals Used by Logic in Function Block
  1: cnt<0>             7: cnt<6>            12: state_FFd1 
  2: cnt<1>             8: cnt<7>            13: state_FFd2 
  3: cnt<2>             9: data<1>           14: state_FFd3 
  4: cnt<3>            10: div_cnt<14>       15: state_FFd4 
  5: cnt<4>            11: nRST              16: state_FFd5 
  6: cnt<5>           

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
state_FFd5           XXXXXXXX.XXXXXXX........................ 15
state_FFd2           XXXXXXXX.XXXXXXX........................ 15
cnt<5>               XXXXXXXX.XXXXXXX........................ 15
cnt<4>               XXXXXXXX.XXXXXXX........................ 15
cnt<1>               XXXXXXXX.XXXXXXX........................ 15
cnt<0>               XXXXXXXX.XXXXXXX........................ 15
cnt<2>               XXXXXXXX.XXXXXXX........................ 15
data<1>              .X......XXXXXXXX........................ 9
cnt<6>               XXXXXXXX.XXXXXXX........................ 15
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********



















































FDCPE_cnt0: FDCPE port map (cnt(0),cnt_D(0),div_cnt(14),NOT nRST,'0');
cnt_D(0) <= ((cnt(1).EXP)
	OR (EXP32_.EXP)
	OR (state_FFd5 AND NOT cnt(0))
	OR (state_FFd3 AND NOT state_FFd1 AND NOT cnt(0))
	OR (NOT state_FFd1 AND state_FFd4 AND NOT cnt(0)));

FTCPE_cnt1: FTCPE port map (cnt(1),cnt_T(1),div_cnt(14),NOT nRST,'0');
cnt_T(1) <= ((EXP31_.EXP)
	OR (NOT state_FFd5 AND NOT state_FFd1 AND state_FFd2)
	OR (NOT cnt(5) AND NOT cnt(1) AND NOT cnt(2) AND NOT cnt(3) AND NOT cnt(4) AND 
	NOT cnt(6) AND NOT cnt(7)));

FTCPE_cnt2: FTCPE port map (cnt(2),EXP34_.EXP,div_cnt(14),'0',NOT nRST);

FTCPE_cnt3: FTCPE port map (cnt(3),cnt_T(3),div_cnt(14),NOT nRST,'0');
cnt_T(3) <= ((EXP12_.EXP)
	OR (EXP13_.EXP)
	OR (state_FFd3 AND NOT state_FFd2)
	OR (NOT state_FFd3 AND state_FFd5)
	OR (state_FFd1 AND NOT state_FFd2));

FTCPE_cnt4: FTCPE port map (cnt(4),cnt_T(4),div_cnt(14),NOT nRST,'0');
cnt_T(4) <= ((EXP30_.EXP)
	OR (state_FFd3 AND state_FFd5 AND state_FFd4 AND 
	state_FFd2 AND cnt(4)));

FTCPE_cnt5: FTCPE port map (cnt(5),EXP29_.EXP,div_cnt(14),NOT nRST,'0');

FTCPE_cnt6: FTCPE port map (cnt(6),cnt_T(6),div_cnt(14),NOT nRST,'0');
cnt_T(6) <= ((data_1.EXP)
	OR (state_FFd3 AND state_FFd5 AND state_FFd4 AND 
	state_FFd2 AND NOT cnt(6))
	OR (NOT state_FFd5 AND state_FFd1 AND state_FFd2 AND NOT cnt(5) AND 
	NOT cnt(0) AND NOT cnt(1) AND NOT cnt(2) AND NOT cnt(3) AND NOT cnt(4) AND cnt(7))
	OR (NOT state_FFd3 AND NOT state_FFd5 AND NOT state_FFd1 AND 
	NOT state_FFd4 AND NOT state_FFd2 AND NOT cnt(5) AND NOT cnt(0) AND NOT cnt(1) AND NOT cnt(2) AND 
	NOT cnt(3) AND NOT cnt(4) AND cnt(7)));

FTCPE_cnt7: FTCPE port map (cnt(7),cnt_T(7),div_cnt(14),'0',NOT nRST);
cnt_T(7) <= ((state_FFd3 AND state_FFd5 AND state_FFd4 AND 
	state_FFd2 AND cnt(7))
	OR (NOT state_FFd5 AND state_FFd1 AND state_FFd2 AND NOT cnt(5) AND 
	NOT cnt(0) AND NOT cnt(1) AND NOT cnt(2) AND NOT cnt(3) AND NOT cnt(4) AND NOT cnt(6) AND 
	cnt(7))
	OR (NOT state_FFd3 AND NOT state_FFd5 AND NOT state_FFd1 AND 
	NOT state_FFd4 AND NOT state_FFd2 AND NOT cnt(5) AND NOT cnt(0) AND NOT cnt(1) AND NOT cnt(2) AND 
	NOT cnt(3) AND NOT cnt(4) AND NOT cnt(6) AND cnt(7)));

FTCPE_data0: FTCPE port map (data(0),data_T(0),div_cnt(14),'0','0',nRST);
data_T(0) <= ((EXP22_.EXP)
	OR (data(0) AND NOT state_FFd3 AND state_FFd5 AND state_FFd1 AND 
	state_FFd4)
	OR (data(0) AND NOT state_FFd3 AND NOT state_FFd5 AND state_FFd4 AND 
	state_FFd2)
	OR (data(0) AND NOT state_FFd3 AND NOT state_FFd1 AND NOT state_FFd4 AND 
	NOT state_FFd2));

FTCPE_data1: FTCPE port map (data(1),data_T(1),div_cnt(14),'0','0',nRST);
data_T(1) <= ((EXP35_.EXP)
	OR (data(1) AND NOT state_FFd3 AND state_FFd5 AND state_FFd1 AND 
	state_FFd4));

FTCPE_data2: FTCPE port map (data(2),data_T(2),div_cnt(14),'0','0',nRST);
data_T(2) <= ((EXP23_.EXP)
	OR (EXP24_.EXP)
	OR (data(2) AND NOT state_FFd3 AND state_FFd5 AND state_FFd1 AND 
	state_FFd4)
	OR (data(2) AND NOT state_FFd3 AND NOT state_FFd5 AND NOT state_FFd4 AND 
	NOT state_FFd2)
	OR (data(2) AND NOT state_FFd5 AND NOT state_FFd1 AND NOT state_FFd4 AND 
	NOT state_FFd2));

FTCPE_data3: FTCPE port map (data(3),data_T(3),div_cnt(14),'0','0',nRST);
data_T(3) <= ((EXP26_.EXP)
	OR (data(3) AND NOT state_FFd3 AND state_FFd5 AND state_FFd1 AND 
	state_FFd4)
	OR (data(3) AND NOT state_FFd3 AND NOT state_FFd5 AND state_FFd4 AND 
	state_FFd2)

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