📄 lcd1.rpt
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cpldfit: version H.42 Xilinx Inc.
Fitter Report
Design Name: lcd1 Date: 2-20-2006, 1:10PM
Device Used: XC95144XL-10-TQ144
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
43 /144 ( 30%) 270 /720 ( 37%) 84 /432 ( 19%) 39 /144 ( 27%) 15 /117 ( 13%)
** Function Block Resources **
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 14/18 16/54 42/90 0/15
FB2 3/18 15/54 25/90 0/15
FB3 0/18 0/54 0/90 0/15
FB4 9/18 16/54 66/90 4/15
FB5 0/18 0/54 0/90 0/14
FB6 8/18 21/54 49/90 8/13
FB7 0/18 0/54 0/90 0/15
FB8 9/18 16/54 88/90 1/15
----- ----- ----- -----
43/144 84/432 270/720 13/117
* - Resource is exhausted
** Global Control Resources **
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 2 2 | I/O : 15 109
Output : 13 13 | GCK/IO : 0 3
Bidirectional : 0 0 | GTS/IO : 0 4
GCK : 0 0 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 15 15
** Power Data **
There are 43 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
************************** Errors and Warnings ***************************
WARNING:Cpld:896 - Unable to map all desired signals into function block, FB6,
because too many function block product terms are required. Buffering output
signal data<7> to allow all signals assigned to this function block to be
placed.
WARNING:Cpld:896 - Unable to map all desired signals into function block, FB6,
because too many function block product terms are required. Buffering output
signal data<5> to allow all signals assigned to this function block to be
placed.
************************* Summary of Mapped Logic ************************
** 13 Outputs **
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
data<6> 13 10 FB4_1 118 I/O O STD FAST RESET
lcd_e 13 8 FB4_2 126 I/O O STD FAST RESET
lcd_rw 0 0 FB4_9 131 I/O O STD FAST
lcd_rs 5 8 FB4_11 132 I/O O STD FAST RESET
data<0> 11 9 FB6_2 106 I/O O STD FAST RESET
data<2> 11 9 FB6_4 111 I/O O STD FAST RESET
data<3> 11 9 FB6_8 113 I/O O STD FAST RESET
data<5> 1 1 FB6_9 116 I/O O STD FAST
data<4> 11 9 FB6_10 115 I/O O STD FAST RESET
data<7> 1 1 FB6_11 119 I/O O STD FAST
lcd_psb 0 0 FB6_12 120 I/O O STD FAST
lcd_RSTB 3 15 FB6_17 125 I/O O STD FAST RESET
data<1> 11 9 FB8_16 107 I/O O STD FAST RESET
** 30 Buried Nodes **
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
div_cnt<9> 3 11 FB1_5 STD RESET
div_cnt<8> 3 10 FB1_6 STD RESET
div_cnt<7> 3 9 FB1_7 STD RESET
div_cnt<6> 3 8 FB1_8 STD RESET
div_cnt<5> 3 7 FB1_9 STD RESET
div_cnt<4> 3 6 FB1_10 STD RESET
div_cnt<3> 3 5 FB1_11 STD RESET
div_cnt<2> 3 4 FB1_12 STD RESET
div_cnt<1> 3 3 FB1_13 STD RESET
div_cnt<14> 3 16 FB1_14 STD RESET
div_cnt<13> 3 15 FB1_15 STD RESET
div_cnt<12> 3 14 FB1_16 STD RESET
div_cnt<11> 3 13 FB1_17 STD RESET
div_cnt<10> 3 12 FB1_18 STD RESET
cnt<7> 5 15 FB2_1 STD RESET
cnt<3> 13 15 FB2_14 STD RESET
state_FFd4 7 15 FB2_16 STD RESET
data<5>_BUFR 11 9 FB4_8 STD RESET
state_FFd1 4 7 FB4_10 STD RESET
state_FFd3 3 4 FB4_12 STD RESET
div_cnt<0> 2 2 FB4_13 STD RESET
data<7>_BUFR 15 11 FB4_15 STD RESET
state_FFd5 8 15 FB8_1 STD RESET
state_FFd2 8 15 FB8_3 STD RESET
cnt<5> 9 15 FB8_5 STD RESET
cnt<4> 11 15 FB8_7 STD RESET
cnt<1> 11 15 FB8_9 STD RESET
cnt<0> 11 15 FB8_10 STD RESET
cnt<2> 12 15 FB8_14 STD RESET
cnt<6> 7 15 FB8_17 STD RESET
** 2 Inputs **
Signal Loc Pin Pin Pin
Name No. Type Use
clk FB4_5 128 I/O I
nRST FB7_2 71 I/O I
Legend:
Pin No. - ~ - User Assigned
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X - Signal used as input to the macrocell logic.
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 16/38
Number of signals used by logic mapping into function block: 16
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB1_1 23 I/O
(unused) 0 0 0 5 FB1_2 16 I/O
(unused) 0 0 0 5 FB1_3 17 I/O
(unused) 0 0 0 5 FB1_4 25 I/O
div_cnt<9> 3 0 0 2 FB1_5 19 I/O (b)
div_cnt<8> 3 0 0 2 FB1_6 20 I/O (b)
div_cnt<7> 3 0 0 2 FB1_7 (b) (b)
div_cnt<6> 3 0 0 2 FB1_8 21 I/O (b)
div_cnt<5> 3 0 0 2 FB1_9 22 I/O (b)
div_cnt<4> 3 0 0 2 FB1_10 31 I/O (b)
div_cnt<3> 3 0 0 2 FB1_11 24 I/O (b)
div_cnt<2> 3 0 0 2 FB1_12 26 I/O (b)
div_cnt<1> 3 0 0 2 FB1_13 (b) (b)
div_cnt<14> 3 0 0 2 FB1_14 27 I/O (b)
div_cnt<13> 3 0 0 2 FB1_15 28 I/O (b)
div_cnt<12> 3 0 0 2 FB1_16 35 I/O (b)
div_cnt<11> 3 0 0 2 FB1_17 30 GCK/I/O (b)
div_cnt<10> 3 0 0 2 FB1_18 (b) (b)
Signals Used by Logic in Function Block
1: clk 7: div_cnt<1> 12: div_cnt<6>
2: div_cnt<0> 8: div_cnt<2> 13: div_cnt<7>
3: div_cnt<10> 9: div_cnt<3> 14: div_cnt<8>
4: div_cnt<11> 10: div_cnt<4> 15: div_cnt<9>
5: div_cnt<12> 11: div_cnt<5> 16: nRST
6: div_cnt<13>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
div_cnt<9> XX....XXXXXXXX.X........................ 11
div_cnt<8> XX....XXXXXXX..X........................ 10
div_cnt<7> XX....XXXXXX...X........................ 9
div_cnt<6> XX....XXXXX....X........................ 8
div_cnt<5> XX....XXXX.....X........................ 7
div_cnt<4> XX....XXX......X........................ 6
div_cnt<3> XX....XX.......X........................ 5
div_cnt<2> XX....X........X........................ 4
div_cnt<1> XX.............X........................ 3
div_cnt<14> XXXXXXXXXXXXXXXX........................ 16
div_cnt<13> XXXXX.XXXXXXXXXX........................ 15
div_cnt<12> XXXX..XXXXXXXXXX........................ 14
div_cnt<11> XXX...XXXXXXXXXX........................ 13
div_cnt<10> XX....XXXXXXXXXX........................ 12
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 15/39
Number of signals used by logic mapping into function block: 15
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
cnt<7> 5 0 0 0 FB2_1 142 I/O (b)
(unused) 0 0 0 5 FB2_2 143 GSR/I/O
(unused) 0 0 0 5 FB2_3 (b)
(unused) 0 0 0 5 FB2_4 4 I/O
(unused) 0 0 0 5 FB2_5 2 GTS/I/O
(unused) 0 0 0 5 FB2_6 3 GTS/I/O
(unused) 0 0 0 5 FB2_7 (b)
(unused) 0 0 0 5 FB2_8 5 GTS/I/O
(unused) 0 0 0 5 FB2_9 6 GTS/I/O
(unused) 0 0 0 5 FB2_10 7 I/O
(unused) 0 0 0 5 FB2_11 9 I/O
(unused) 0 0 0 5 FB2_12 10 I/O
(unused) 0 0 \/3 2 FB2_13 12 I/O (b)
cnt<3> 13 8<- 0 0 FB2_14 11 I/O (b)
(unused) 0 0 /\5 0 FB2_15 13 I/O (b)
state_FFd4 7 2<- 0 0 FB2_16 14 I/O (b)
(unused) 0 0 /\2 3 FB2_17 15 I/O (b)
(unused) 0 0 0 5 FB2_18 (b)
Signals Used by Logic in Function Block
1: cnt<0> 6: cnt<5> 11: state_FFd1
2: cnt<1> 7: cnt<6> 12: state_FFd2
3: cnt<2> 8: cnt<7> 13: state_FFd3
4: cnt<3> 9: div_cnt<14> 14: state_FFd4
5: cnt<4> 10: nRST 15: state_FFd5
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
cnt<7> XXXXXXXXXXXXXXX......................... 15
cnt<3> XXXXXXXXXXXXXXX......................... 15
state_FFd4 XXXXXXXXXXXXXXX......................... 15
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 0/54
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB3_1 39 I/O
(unused) 0 0 0 5 FB3_2 32 GCK/I/O
(unused) 0 0 0 5 FB3_3 41 I/O
(unused) 0 0 0 5 FB3_4 44 I/O
(unused) 0 0 0 5 FB3_5 33 I/O
(unused) 0 0 0 5 FB3_6 34 I/O
(unused) 0 0 0 5 FB3_7 46 I/O
(unused) 0 0 0 5 FB3_8 38 GCK/I/O
(unused) 0 0 0 5 FB3_9 40 I/O
(unused) 0 0 0 5 FB3_10 48 I/O
(unused) 0 0 0 5 FB3_11 43 I/O
(unused) 0 0 0 5 FB3_12 45 I/O
(unused) 0 0 0 5 FB3_13 (b)
(unused) 0 0 0 5 FB3_14 49 I/O
(unused) 0 0 0 5 FB3_15 50 I/O
(unused) 0 0 0 5 FB3_16 (b)
(unused) 0 0 0 5 FB3_17 51 I/O
(unused) 0 0 0 5 FB3_18 (b)
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 16/38
Number of signals used by logic mapping into function block: 16
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
data<6> 13 9<- \/1 0 FB4_1 118 I/O O
lcd_e 13 8<- 0 0 FB4_2 126 I/O O
(unused) 0 0 /\5 0 FB4_3 133 I/O (b)
(unused) 0 0 /\2 3 FB4_4 (b) (b)
(unused) 0 0 0 5 FB4_5 128 I/O I
(unused) 0 0 0 5 FB4_6 129 I/O
(unused) 0 0 \/5 0 FB4_7 (b) (b)
data<5>_BUFR 11 6<- 0 0 FB4_8 130 I/O (b)
lcd_rw 0 0 /\1 4 FB4_9 131 I/O O
state_FFd1 4 0 0 1 FB4_10 135 I/O (b)
lcd_rs 5 0 0 0 FB4_11 132 I/O O
state_FFd3 3 0 0 2 FB4_12 134 I/O (b)
div_cnt<0> 2 0 0 3 FB4_13 137 I/O (b)
(unused) 0 0 \/5 0 FB4_14 136 I/O (b)
data<7>_BUFR 15 10<- 0 0 FB4_15 138 I/O (b)
(unused) 0 0 /\5 0 FB4_16 139 I/O (b)
(unused) 0 0 \/4 1 FB4_17 140 I/O (b)
(unused) 0 0 \/5 0 FB4_18 (b) (b)
Signals Used by Logic in Function Block
1: clk 7: data<7>_BUFR 12: state_FFd1
2: cnt<5> 8: div_cnt<14> 13: state_FFd2
3: cnt<6> 9: lcd_e 14: state_FFd3
4: cnt<7> 10: lcd_rs 15: state_FFd4
5: data<5>_BUFR 11: nRST 16: state_FFd5
6: data<6>
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