lcd1.syr

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <lcd1> ...
Loading device for application Rf_Device from file 'v50.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block lcd1, actual ratio is 6.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : lcd1.ngr
Top Level Output File Name         : lcd1
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 13

Macro Statistics :
# Registers                        : 12
#      1-bit register              : 10
#      15-bit register             : 1
#      8-bit register              : 1
# Adders/Subtractors               : 2
#      15-bit adder                : 1
#      8-bit subtractor            : 1

Cell Usage :
# BELS                             : 129
#      GND                         : 1
#      INV                         : 9
#      LUT1                        : 13
#      LUT1_L                      : 2
#      LUT2                        : 9
#      LUT2_L                      : 4
#      LUT3                        : 1
#      LUT3_L                      : 3
#      LUT4                        : 9
#      LUT4_D                      : 3
#      LUT4_L                      : 24
#      MUXCY                       : 21
#      MUXF5                       : 7
#      VCC                         : 1
#      XORCY                       : 22
# FlipFlops/Latches                : 59
#      FDC                         : 30
#      FDC_1                       : 15
#      FDE                         : 10
#      FDP                         : 4
# Clock Buffers                    : 2
#      BUFG                        : 1
#      BUFGP                       : 1
# IO Buffers                       : 12
#      IBUF                        : 1
#      OBUF                        : 11
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-5 

 Number of Slices:                      48  out of    768     6%  
 Number of Slice Flip Flops:            59  out of   1536     3%  
 Number of 4 input LUTs:                68  out of   1536     4%  
 Number of bonded IOBs:                 13  out of     96    13%  
 Number of GCLKs:                        2  out of      4    50%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
div_cnt_14:Q                       | BUFG                   | 44    |
clk                                | BUFGP                  | 15    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 9.453ns (Maximum Frequency: 105.787MHz)
   Minimum input arrival time before clock: 4.110ns
   Maximum output required time after clock: 8.189ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'div_cnt_14:Q'
  Clock period: 8.944ns (frequency: 111.807MHz)
  Total number of paths / destination ports: 336 / 43
-------------------------------------------------------------------------
Delay:               8.944ns (Levels of Logic = 3)
  Source:            state_FFd15 (FF)
  Destination:       data_6 (FF)
  Source Clock:      div_cnt_14:Q rising
  Destination Clock: div_cnt_14:Q rising

  Data Path: state_FFd15 to data_6
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              5   1.292   1.740  state_FFd15 (state_FFd15)
     LUT3:I1->O            1   0.653   1.150  _n003514_SW0 (N251)
     LUT4:I3->O            8   0.653   2.050  _n003514 (_n0035)
     LUT4_L:I0->LO         1   0.653   0.000  _n0029<6> (_n0029<6>)
     FDE:D                     0.753          data_6
    ----------------------------------------
    Total                      8.944ns (4.004ns logic, 4.940ns route)
                                       (44.8% logic, 55.2% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 9.453ns (frequency: 105.787MHz)
  Total number of paths / destination ports: 120 / 15
-------------------------------------------------------------------------
Delay:               9.453ns (Levels of Logic = 3)
  Source:            div_cnt_14 (FF)
  Destination:       div_cnt_14 (FF)
  Source Clock:      clk falling
  Destination Clock: clk falling

  Data Path: div_cnt_14 to div_cnt_14
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q            1   1.292   1.150  div_cnt_14 (div_cnt_141)
     BUFG:I->O            45   0.773   4.450  div_cnt_14_BUFG (div_cnt_14)
     LUT1_L:I0->LO         0   0.653   0.000  div_cnt_14_rt (div_cnt_14_rt)
     XORCY:LI->O           1   0.382   0.000  lcd1_div_cnt__n0000<14>_xor (div_cnt__n0000<14>)
     FDC_1:D                   0.753          div_cnt_14
    ----------------------------------------
    Total                      9.453ns (3.853ns logic, 5.600ns route)
                                       (40.8% logic, 59.2% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'div_cnt_14:Q'
  Total number of paths / destination ports: 10 / 10
-------------------------------------------------------------------------
Offset:              4.110ns (Levels of Logic = 1)
  Source:            nRST (PAD)
  Destination:       data_6 (FF)
  Destination Clock: div_cnt_14:Q rising

  Data Path: nRST to data_6
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            11   0.924   2.300  nRST_IBUF (nRST_IBUF)
     FDE:CE                    0.886          data_2
    ----------------------------------------
    Total                      4.110ns (1.810ns logic, 2.300ns route)
                                       (44.0% logic, 56.0% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'div_cnt_14:Q'
  Total number of paths / destination ports: 10 / 10
-------------------------------------------------------------------------
Offset:              8.189ns (Levels of Logic = 1)
  Source:            lcd_e (FF)
  Destination:       lcd_e (PAD)
  Source Clock:      div_cnt_14:Q rising

  Data Path: lcd_e to lcd_e
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              2   1.292   1.340  lcd_e (lcd_e_OBUF)
     OBUF:I->O                 5.557          lcd_e_OBUF (lcd_e)
    ----------------------------------------
    Total                      8.189ns (6.849ns logic, 1.340ns route)
                                       (83.6% logic, 16.4% route)

=========================================================================
CPU : 10.30 / 11.03 s | Elapsed : 11.00 / 11.00 s
 
--> 

Total memory usage is 75780 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    1 (   0 filtered)