📄 lcd1.syr
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Release 7.1.04i - xst H.42Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.--> Parameter TMPDIR set to __projnavCPU : 0.00 / 0.63 s | Elapsed : 0.00 / 0.00 s --> Parameter xsthdpdir set to ./xstCPU : 0.00 / 0.63 s | Elapsed : 0.00 / 0.00 s --> Reading design: lcd1.prjTABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) HDL Analysis 4) HDL Synthesis 5) Advanced HDL Synthesis 5.1) HDL Synthesis Report 6) Low Level Synthesis 7) Final Report 7.1) Device utilization summary 7.2) TIMING REPORT=========================================================================* Synthesis Options Summary *=========================================================================---- Source ParametersInput File Name : "lcd1.prj"Input Format : mixedIgnore Synthesis Constraint File : NO---- Target ParametersOutput File Name : "lcd1"Output Format : NGCTarget Device : xc2s50-5-TQ144---- Source OptionsTop Module Name : lcd1Automatic FSM Extraction : YESFSM Encoding Algorithm : AutoFSM Style : lutRAM Extraction : YesRAM Style : AutoROM Extraction : YesROM Style : AutoMux Extraction : YESMux Style : AutoDecoder Extraction : YESPriority Encoder Extraction : YESShift Register Extraction : YESLogical Shifter Extraction : YESXOR Collapsing : YESResource Sharing : YESMultiplier Style : lutAutomatic Register Balancing : No---- Target OptionsAdd IO Buffers : YESGlobal Maximum Fanout : 100Add Generic Clock Buffer(BUFG) : 4Register Duplication : YESEquivalent register Removal : YESSlice Packing : YESPack IO Registers into IOBs : auto---- General OptionsOptimization Goal : SpeedOptimization Effort : 1Keep Hierarchy : NOGlobal Optimization : AllClockNetsRTL Output : YesWrite Timing Constraints : NOHierarchy Separator : /Bus Delimiter : <>Case Specifier : maintainSlice Utilization Ratio : 100Slice Utilization Ratio Delta : 5---- Other Optionslso : lcd1.lsoRead Cores : YEScross_clock_analysis : NOverilog2001 : YESsafe_implementation : NoOptimize Instantiated Primitives : NOtristate2logic : Yesuse_clock_enable : Yesuse_sync_set : Yesuse_sync_reset : Yesenable_auto_floorplanning : No==================================================================================================================================================* HDL Compilation *=========================================================================Compiling vhdl file "E:/temp/SPARTAN2/vhdl/Interface/lcd12864/lcd1.vhd" in Library work.Entity <lcd1> compiled.Entity <lcd1> (Architecture <behave>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <lcd1> (Architecture <behave>).INFO:Xst:1304 - Contents of register <lcd_rw> in unit <lcd1> never changes during circuit operation. The register is replaced by logic.Entity <lcd1> analyzed. Unit <lcd1> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <lcd1>. Related source file is "E:/temp/SPARTAN2/vhdl/Interface/lcd12864/lcd1.vhd". Found finite state machine <FSM_0> for signal <state>. ----------------------------------------------------------------------- | States | 26 | | Transitions | 27 | | Inputs | 1 | | Outputs | 25 | | Clock | clk_div (rising_edge) | | Reset | nRST (negative) | | Reset type | asynchronous | | Reset State | 00001 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found 1-bit register for signal <lcd_rs>. Found 1-bit register for signal <lcd_e>. Found 8-bit register for signal <data>. Found 8-bit subtractor for signal <$n0031> created at line 217. Found 8-bit adder for signal <$n0032> created at line 203. Found 8-bit register for signal <cnt>. Found 15-bit up counter for signal <div_cnt>. Summary: inferred 1 Finite State Machine(s). inferred 1 Counter(s). inferred 10 D-type flip-flop(s). inferred 2 Adder/Subtractor(s).Unit <lcd1> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Analyzing FSM <FSM_0> for best encoding.Optimizing FSM <FSM_0> on signal <state[1:26]> with speed1 encoding.------------------------------------- State | Encoding------------------------------------- 00001 | 10000000001000000000000000 00010 | 01000000000000000000000000 00011 | 00100000000000000000000000 00100 | 00010000000000000000000000 00101 | 00001000000000000000000000 00110 | 00000100000000000000000000 00111 | 00000010000000000000000000 01000 | 00000001000000000000000000 01001 | 00000000100000000000000000 01010 | 00000000010000000000000000 01011 | 00000000000100000000000000 01100 | 00000000000010000000000000 01101 | 00000000000001000000000000 01110 | 00000000000000000001000000 01111 | 00000000000000000000010000 10000 | 00000000000000000000000100 10001 | 00000000000000000000000010 10010 | 00000000000000001000000000 10011 | 00000000000000000010000000 10100 | 00000000000000000000100000 10101 | 00000000000000000000001000 10110 | 00000000000000000000000001 10111 | 00000000001000000000000000 11000 | 00000000000000100000000000 11001 | 00000000000000010000000000 11010 | 00000000000000000100000000-------------------------------------Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# FSMs : 1# Adders/Subtractors : 2 8-bit adder : 1 8-bit subtractor : 1# Counters : 1 15-bit up counter : 1# Registers : 30 1-bit register : 28 8-bit register : 2==================================================================================================================================================⌨️ 快捷键说明
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