lcd.rpt

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

data_6_OBUFE/data_6_OBUFE_TRST
                      7       2<-   0   0     FB8_8   94    I/O     (b)
(unused)              0       0   /\2   3     FB8_9   96    I/O     (b)
(unused)              0       0   \/5   0     FB8_10  101   I/O     (b)
data<5>_BUFR         15      10<-   0   0     FB8_11  98    I/O     (b)
(unused)              0       0   /\5   0     FB8_12  100   I/O     (b)
(unused)              0       0     0   5     FB8_13  103   I/O     
(unused)              0       0   \/5   0     FB8_14  102   I/O     (b)
(unused)              0       0   \/5   0     FB8_15  104   I/O     (b)
data<1>              21      16<-   0   0     FB8_16  107   I/O     O
(unused)              0       0   /\5   0     FB8_17  105   I/O     (b)
state<2>              3       0   /\1   1     FB8_18        (b)     (b)

Signals Used by Logic in Function Block
  1: Msub__n0029__n0005   8: counter<5>                      15: state<0> 
  2: Reset                9: counter<6>                      16: state<2> 
  3: clk_int             10: data_6_OBUFE/data_6_OBUFE_TRST  17: state<3> 
  4: counter<1>          11: div_counter<0>                  18: state<4> 
  5: counter<2>          12: div_counter<1>                  19: state<5> 
  6: counter<3>          13: div_counter<2>                  20: state<7> 
  7: counter<4>          14: flag                            21: state<9> 

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
state<5>             .XX..........XXXXXXXX................... 10
state<3>             .XX...........XXXXXXX................... 9
state<0>             .XX...........XXXXXXX................... 9
flag                 .XX..........XXXXXXXX................... 10
div_counter<0>       .XX.......X..XXXXXXXX................... 11
div_counter<2>       .XX.......XXXXXXXXXXX................... 13
div_counter<1>       .XX.......XX.XXXXXXXX................... 12
data_6_OBUFE/data_6_OBUFE_TRST 
                     ..............XXXXXXX................... 7
data<5>_BUFR         X..XXXXXX.....XXXXXXX................... 14
data<1>              X..XXXXXXX....XXXXXXX................... 15
state<2>             .XX...........XXXXXXX................... 9
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********







































FTCPE_Msub__n0029__n0005: FTCPE port map (Msub__n0029__n0005,Msub__n0029__n0005_T,clk_int,NOT Reset,'0');
Msub__n0029__n0005_T <= ((lcd_rs_OBUF.EXP)
	OR (NOT state(7) AND state(9) AND NOT state(5) AND NOT state(4) AND 
	NOT state(2) AND NOT state(3) AND NOT state(0) AND NOT counter(6))
	OR (NOT state(7) AND state(9) AND NOT state(5) AND NOT state(4) AND 
	NOT state(2) AND NOT state(3) AND NOT state(0) AND NOT counter(4) AND NOT counter(5)));

FTCPE_clk_int: FTCPE port map (clk_int,'1',clkdiv,NOT Reset,'0');

FTCPE_clkcnt0: FTCPE port map (clkcnt(0),clkcnt_T(0),clk,NOT Reset,'0');
clkcnt_T(0) <= (NOT clkcnt(0) AND clkcnt(10) AND clkcnt(11) AND 
	clkcnt(12) AND NOT clkcnt(13) AND NOT clkcnt(14) AND clkcnt(15) AND 
	clkcnt(16) AND clkcnt(17) AND NOT clkcnt(1) AND NOT clkcnt(2) AND NOT clkcnt(3) AND 
	NOT clkcnt(4) AND NOT clkcnt(5) AND clkcnt(6) AND NOT clkcnt(7) AND NOT clkcnt(8) AND 
	NOT clkcnt(9) AND clkcnt(18));

FTCPE_clkcnt1: FTCPE port map (clkcnt(1),clkcnt(0),clk,NOT Reset,'0');

FTCPE_clkcnt2: FTCPE port map (clkcnt(2),clkcnt_T(2),clk,NOT Reset,'0');
clkcnt_T(2) <= (clkcnt(0) AND clkcnt(1));

FTCPE_clkcnt3: FTCPE port map (clkcnt(3),clkcnt_T(3),clk,NOT Reset,'0');
clkcnt_T(3) <= (clkcnt(0) AND clkcnt(1) AND clkcnt(2));

FTCPE_clkcnt4: FTCPE port map (clkcnt(4),clkcnt_T(4),clk,NOT Reset,'0');
clkcnt_T(4) <= (clkcnt(0) AND clkcnt(1) AND clkcnt(2) AND clkcnt(3));

FTCPE_clkcnt5: FTCPE port map (clkcnt(5),clkcnt_T(5),clk,NOT Reset,'0');
clkcnt_T(5) <= (clkcnt(0) AND clkcnt(1) AND clkcnt(2) AND clkcnt(3) AND 
	clkcnt(4));

FTCPE_clkcnt6: FTCPE port map (clkcnt(6),clkcnt_T(6),clk,NOT Reset,'0');
clkcnt_T(6) <= ((clkcnt(0) AND clkcnt(1) AND clkcnt(2) AND clkcnt(3) AND 
	clkcnt(4) AND clkcnt(5))
	OR (NOT clkcnt(0) AND clkcnt(10) AND clkcnt(11) AND 
	clkcnt(12) AND NOT clkcnt(13) AND NOT clkcnt(14) AND clkcnt(15) AND 
	clkcnt(16) AND clkcnt(17) AND NOT clkcnt(1) AND NOT clkcnt(2) AND NOT clkcnt(3) AND 
	NOT clkcnt(4) AND NOT clkcnt(5) AND clkcnt(6) AND NOT clkcnt(7) AND NOT clkcnt(8) AND 
	NOT clkcnt(9) AND clkcnt(18)));

FTCPE_clkcnt7: FTCPE port map (clkcnt(7),clkcnt_T(7),clk,NOT Reset,'0');
clkcnt_T(7) <= (clkcnt(0) AND clkcnt(1) AND clkcnt(2) AND clkcnt(3) AND 
	clkcnt(4) AND clkcnt(5) AND clkcnt(6));

FTCPE_clkcnt8: FTCPE port map (clkcnt(8),clkcnt_T(8),clk,NOT Reset,'0');
clkcnt_T(8) <= (clkcnt(0) AND clkcnt(1) AND clkcnt(2) AND clkcnt(3) AND 
	clkcnt(4) AND clkcnt(5) AND clkcnt(6) AND clkcnt(7));

FTCPE_clkcnt9: FTCPE port map (clkcnt(9),clkcnt_T(9),clk,NOT Reset,'0');
clkcnt_T(9) <= (clkcnt(0) AND clkcnt(1) AND clkcnt(2) AND clkcnt(3) AND 
	clkcnt(4) AND clkcnt(5) AND clkcnt(6) AND clkcnt(7) AND clkcnt(8));

FTCPE_clkcnt10: FTCPE port map (clkcnt(10),clkcnt_T(10),clk,NOT Reset,'0');
clkcnt_T(10) <= ((clkcnt(0) AND clkcnt(1) AND clkcnt(2) AND clkcnt(3) AND 
	clkcnt(4) AND clkcnt(5) AND clkcnt(6) AND clkcnt(7) AND clkcnt(8) AND 
	clkcnt(9))
	OR (NOT clkcnt(0) AND clkcnt(10) AND clkcnt(11) AND 
	clkcnt(12) AND NOT clkcnt(13) AND NOT clkcnt(14) AND clkcnt(15) AND 
	clkcnt(16) AND clkcnt(17) AND NOT clkcnt(1) AND NOT clkcnt(2) AND NOT clkcnt(3) AND 
	NOT clkcnt(4) AND NOT clkcnt(5) AND clkcnt(6) AND NOT clkcnt(7) AND NOT clkcnt(8) AND 
	NOT clkcnt(9) AND clkcnt(18)));

FTCPE_clkcnt11: FTCPE port map (clkcnt(11),clkcnt_T(11),clk,NOT Reset,'0');
clkcnt_T(11) <= ((clkcnt(0) AND clkcnt(10) AND clkcnt(1) AND clkcnt(2) AND 
	clkcnt(3) AND clkcnt(4) AND clkcnt(5) AND clkcnt(6) AND clkcnt(7) AND 
	clkcnt(8) AND clkcnt(9))
	OR (NOT clkcnt(0) AND clkcnt(10) AND clkcnt(11) AND 
	clkcnt(12) AND NOT clkcnt(13) AND NOT clkcnt(14) AND clkcnt(15) AND 
	clkcnt(16) AND clkcnt(17) AND NOT clkcnt(1) AND NOT clkcnt(2) AND NOT clkcnt(3) AND 
	NOT clkcnt(4) AND NOT clkcnt(5) AND clkcnt(6) AND NOT clkcnt(7) AND NOT clkcnt(8) AND 
	NOT clkcnt(9) AND clkcnt(18)));

FTCPE_clkcnt12: FTCPE port map (clkcnt(12),clkcnt_T(12),clk,NOT Reset,'0');
clkcnt_T(12) <= ((clkcnt(0) AND clkcnt(10) AND clkcnt(11) AND clkcnt(1) AND 
	clkcnt(2) AND clkcnt(3) AND clkcnt(4) AND clkcnt(5) AND clkcnt(6) AND 
	clkcnt(7) AND clkcnt(8) AND clkcnt(9))
	OR (NOT clkcnt(0) AND clkcnt(10) AND clkcnt(11) AND 
	clkcnt(12) AND NOT clkcnt(13) AND NOT clkcnt(14) AND clkcnt(15) AND 
	clkcnt(16) AND clkcnt(17) AND NOT clkcnt(1) AND NOT clkcnt(2) AND NOT clkcnt(3) AND 
	NOT clkcnt(4) AND NOT clkcnt(5) AND clkcnt(6) AND NOT clkcnt(7) AND NOT clkcnt(8) AND 
	NOT clkcnt(9) AND clkcnt(18)));

FTCPE_clkcnt13: FTCPE port map (clkcnt(13),clkcnt_T(13),clk,NOT Reset,'0');
clkcnt_T(13) <= (clkcnt(0) AND clkcnt(10) AND clkcnt(11) AND 
	clkcnt(12) AND clkcnt(1) AND clkcnt(2) AND clkcnt(3) AND clkcnt(4) AND 
	clkcnt(5) AND clkcnt(6) AND clkcnt(7) AND clkcnt(8) AND clkcnt(9));

FTCPE_clkcnt14: FTCPE port map (clkcnt(14),clkcnt_T(14),clk,NOT Reset,'0');
clkcnt_T(14) <= (clkcnt(0) AND clkcnt(10) AND clkcnt(11) AND 
	clkcnt(12) AND clkcnt(13) AND clkcnt(1) AND clkcnt(2) AND clkcnt(3) AND 
	clkcnt(4) AND clkcnt(5) AND clkcnt(6) AND clkcnt(7) AND clkcnt(8) AND 
	clkcnt(9));

FTCPE_clkcnt15: FTCPE port map (clkcnt(15),clkcnt_T(15),clk,NOT Reset,'0');
clkcnt_T(15) <= ((clkcnt(0) AND clkcnt(10) AND clkcnt(11) AND 
	clkcnt(12) AND clkcnt(13) AND clkcnt(14) AND clkcnt(1) AND clkcnt(2) AND 
	clkcnt(3) AND clkcnt(4) AND clkcnt(5) AND clkcnt(6) AND clkcnt(7) AND 
	clkcnt(8) AND clkcnt(9))
	OR (NOT clkcnt(0) AND clkcnt(10) AND clkcnt(11) AND 
	clkcnt(12) AND NOT clkcnt(13) AND NOT clkcnt(14) AND clkcnt(15) AND 
	clkcnt(16) AND clkcnt(17) AND NOT clkcnt(1) AND NOT clkcnt(2) AND NOT clkcnt(3) AND 
	NOT clkcnt(4) AND NOT clkcnt(5) AND clkcnt(6) AND NOT clkcnt(7) AND NOT clkcnt(8) AND 
	NOT clkcnt(9) AND clkcnt(18)));

FTCPE_clkcnt16: FTCPE port map (clkcnt(16),clkcnt_T(16),clk,NOT Reset,'0');
clkcnt_T(16) <= ((clkcnt(0) AND clkcnt(10) AND clkcnt(11) AND 
	clkcnt(12) AND clkcnt(13) AND clkcnt(14) AND clkcnt(15) AND 
	clkcnt(1) AND clkcnt(2) AND clkcnt(3) AND clkcnt(4) AND clkcnt(5) AND 
	clkcnt(6) AND clkcnt(7) AND clkcnt(8) AND clkcnt(9))
	OR (NOT clkcnt(0) AND clkcnt(10) AND clkcnt(11) AND 
	clkcnt(12) AND NOT clkcnt(13) AND NOT clkcnt(14) AND clkcnt(15) AND 
	clkcnt(16) AND clkcnt(17) AND NOT clkcnt(1) AND NOT clkcnt(2) AND NOT clkcnt(3) AND 
	NOT clkcnt(4) AND NOT clkcnt(5) AND clkcnt(6) AND NOT clkcnt(7) AND NOT clkcnt(8) AND 
	NOT clkcnt(9) AND clkcnt(18)));

FTCPE_clkcnt17: FTCPE port map (clkcnt(17),clkcnt_T(17),clk,NOT Reset,'0');
clkcnt_T(17) <= ((clkcnt(0) AND clkcnt(10) AND clkcnt(11) AND 
	clkcnt(12) AND clkcnt(13) AND clkcnt(14) AND clkcnt(15) AND 
	clkcnt(16) AND clkcnt(1) AND clkcnt(2) AND clkcnt(3) AND clkcnt(4) AND 
	clkcnt(5) AND clkcnt(6) AND clkcnt(7) AND clkcnt(8) AND clkcnt(9))
	OR (NOT clkcnt(0) AND clkcnt(10) AND clkcnt(11) AND 
	clkcnt(12) AND NOT clkcnt(13) AND NOT clkcnt(14) AND clkcnt(15) AND 
	clkcnt(16) AND clkcnt(17) AND NOT clkcnt(1) AND NOT clkcnt(2) AND NOT clkcnt(3) AND 
	NOT clkcnt(4) AND NOT clkcnt(5) AND clkcnt(6) AND NOT clkcnt(7) AND NOT clkcnt(8) AND 
	NOT clkcnt(9) AND clkcnt(18)));

FTCPE_clkcnt18: FTCPE port map (clkcnt(18),clkcnt_T(18),clk,NOT Reset,'0');
clkcnt_T(18) <= ((clkcnt(0) AND clkcnt(10) AND clkcnt(11) AND 
	clkcnt(12) AND clkcnt(13) AND clkcnt(14) AND clkcnt(15) AND 
	clkcnt(16) AND clkcnt(17) AND clkcnt(1) AND clkcnt(2) AND clkcnt(3) AND 
	clkcnt(4) AND clkcnt(5) AND clkcnt(6) AND clkcnt(7) AND clkcnt(8) AND 
	clkcnt(9))
	OR (NOT clkcnt(0) AND clkcnt(10) AND clkcnt(11) AND 
	clkcnt(12) AND NOT clkcnt(13) AND NOT clkcnt(14) AND clkcnt(15) AND 
	clkcnt(16) AND clkcnt(17) AND NOT clkcnt(1) AND NOT clkcnt(2) AND NOT clkcnt(3) AND 
	NOT clkcnt(4) AND NOT clkcnt(5) AND clkcnt(6) AND NOT clkcnt(7) AND NOT clkcnt(8) AND 
	NOT clkcnt(9) AND clkcnt(18)));

FTCPE_clkdiv: FTCPE port map (clkdiv,'1',clkdiv_C,NOT Reset,'0');
clkdiv_C <= (NOT clkcnt(0) AND clkcnt(10) AND clkcnt(11) AND 
	clkcnt(12) AND NOT clkcnt(13) AND NOT clkcnt(14) AND clkcnt(15) AND 
	clkcnt(16) AND clkcnt(17) AND NOT clkcnt(1) AND NOT clkcnt(2) AND NOT clkcnt(3) AND 
	NOT clkcnt(4) AND NOT clkcnt(5) AND clkcnt(6) AND NOT clkcnt(7) AND NOT clkcnt(8) AND 
	NOT clkcnt(9) AND clkcnt(18));