lcd.rpt

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

 
cpldfit:  version H.42                              Xilinx Inc.
                                  Fitter Report
Design Name: lcd                                 Date:  2-20-2006, 12:50PM
Device Used: XC95144XL-10-TQ144
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
56 /144 ( 39%) 307 /720  ( 43%) 108/432 ( 25%)   41 /144 ( 28%) 13 /117 ( 11%)

** Function Block Resources **

Function    Mcells      FB Inps     Pterms      IO          
Block       Used/Tot    Used/Tot    Used/Tot    Used/Tot    
FB1           2/18       21/54       13/90       0/15
FB2          18/18*      21/54       61/90       0/15
FB3           3/18        5/54        8/90       0/15
FB4          12/18       19/54       78/90       4/15
FB5           0/18        0/54        0/90       0/14
FB6          10/18       21/54       75/90       6/13
FB7           0/18        0/54        0/90       0/15
FB8          11/18       21/54       72/90       1/15
             -----       -----       -----      -----    
             56/144     108/432     307/720     11/117

* - Resource is exhausted

** Global Control Resources **

Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :    2           2    |  I/O              :    13     109
Output        :   11          11    |  GCK/IO           :     0       3
Bidirectional :    0           0    |  GTS/IO           :     0       4
GCK           :    0           0    |  GSR/IO           :     0       1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     13          13

** Power Data **

There are 56 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
**************************  Errors and Warnings  ***************************

WARNING:Cpld:896 - Unable to map all desired signals into function block, FB6,
   because too many function block product terms are required. Buffering output
   signal data<0> to allow all signals assigned to this function block to be
   placed.
WARNING:Cpld:896 - Unable to map all desired signals into function block, FB6,
   because too many function block product terms are required. Buffering output
   signal data<4> to allow all signals assigned to this function block to be
   placed.
WARNING:Cpld:896 - Unable to map all desired signals into function block, FB6,
   because too many function block product terms are required. Buffering output
   signal data<2> to allow all signals assigned to this function block to be
   placed.
WARNING:Cpld:896 - Unable to map all desired signals into function block, FB6,
   because too many function block product terms are required. Buffering output
   signal data<5> to allow all signals assigned to this function block to be
   placed.
*************************  Summary of Mapped Logic  ************************

** 11 Outputs **

Signal                          Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                            Pts   Inps          No.  Type    Use     Mode Rate State
data<6>                         18    15    FB4_1   118  I/O     O       STD  FAST 
lcd_e                           2     2     FB4_2   126  I/O     O       STD  FAST RESET
lcd_rw                          7     7     FB4_9   131  I/O     O       STD  FAST 
lcd_rs                          1     7     FB4_11  132  I/O     O       STD  FAST 
data<0>                         2     2     FB6_2   106  I/O     O       STD  FAST 
data<2>                         2     2     FB6_4   111  I/O     O       STD  FAST 
data<3>                         12    15    FB6_8   113  I/O     O       STD  FAST 
data<5>                         2     2     FB6_9   116  I/O     O       STD  FAST 
data<4>                         2     2     FB6_10  115  I/O     O       STD  FAST 
data<7>                         2     8     FB6_11  119  I/O     O       STD  FAST 
data<1>                         21    15    FB8_16  107  I/O     O       STD  FAST 

** 45 Buried Nodes **

Signal                          Total Total Loc     Pwr  Reg Init
Name                            Pts   Inps          Mode State
div_counter<3>                  5     14    FB1_17  STD  RESET
state<4>                        8     21    FB1_18  STD  RESET
clkdiv                          2     20    FB2_1   STD  RESET
clkcnt<9>                       3     11    FB2_2   STD  RESET
clkcnt<8>                       3     10    FB2_3   STD  RESET
clkcnt<7>                       3     9     FB2_4   STD  RESET
clkcnt<5>                       3     7     FB2_5   STD  RESET
clkcnt<4>                       3     6     FB2_6   STD  RESET
clkcnt<3>                       3     5     FB2_7   STD  RESET
clkcnt<14>                      3     16    FB2_8   STD  RESET
clkcnt<13>                      3     15    FB2_9   STD  RESET
clkcnt<0>                       3     21    FB2_10  STD  RESET
clkcnt<6>                       4     21    FB2_11  STD  RESET
clkcnt<18>                      4     21    FB2_12  STD  RESET
clkcnt<17>                      4     21    FB2_13  STD  RESET
clkcnt<16>                      4     21    FB2_14  STD  RESET
clkcnt<15>                      4     21    FB2_15  STD  RESET
clkcnt<12>                      4     21    FB2_16  STD  RESET
clkcnt<11>                      4     21    FB2_17  STD  RESET
clkcnt<10>                      4     21    FB2_18  STD  RESET
clk_int                         2     2     FB3_16  STD  RESET
clkcnt<2>                       3     4     FB3_17  STD  RESET
clkcnt<1>                       3     3     FB3_18  STD  RESET
counter<3>                      5     17    FB4_3   STD  RESET
counter<4>                      5     17    FB4_4   STD  RESET
counter<5>                      4     17    FB4_5   STD  RESET
counter<6>                      4     17    FB4_6   STD  RESET
counter<2>                      5     16    FB4_10  STD  RESET
Msub__n0029__n0005              6     17    FB4_12  STD  RESET
data<2>_BUFR                    16    14    FB4_14  STD  
counter<1>                      5     15    FB4_16  STD  RESET
state<9>                        11    16    FB6_3   STD  RESET
state<7>                        3     16    FB6_5   STD  RESET
data<4>_BUFR                    18    14    FB6_13  STD  
data<0>_BUFR                    21    14    FB6_17  STD  
state<5>                        3     10    FB8_1   STD  RESET
state<3>                        3     9     FB8_2   STD  RESET
state<0>                        3     9     FB8_3   STD  RESET
flag                            3     10    FB8_4   STD  RESET
div_counter<0>                  4     11    FB8_5   STD  RESET

Signal                          Total Total Loc     Pwr  Reg Init
Name                            Pts   Inps          Mode State
div_counter<2>                  5     13    FB8_6   STD  RESET
div_counter<1>                  5     12    FB8_7   STD  RESET
data_6_OBUFE/data_6_OBUFE_TRST  7     7     FB8_8   STD  
data<5>_BUFR                    15    14    FB8_11  STD  
state<2>                        3     9     FB8_18  STD  RESET

** 2 Inputs **

Signal                          Loc     Pin  Pin     Pin     
Name                                    No.  Type    Use     
clk                             FB4_5   128  I/O     I
Reset                           FB7_2   71   I/O     I

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X            - Signal used as input to the macrocell logic.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               21/33
Number of signals used by logic mapping into function block:  21
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0   /\3   2     FB1_1   23    I/O     (b)
(unused)              0       0     0   5     FB1_2   16    I/O     
(unused)              0       0     0   5     FB1_3   17    I/O     
(unused)              0       0     0   5     FB1_4   25    I/O     
(unused)              0       0     0   5     FB1_5   19    I/O     
(unused)              0       0     0   5     FB1_6   20    I/O     
(unused)              0       0     0   5     FB1_7         (b)     
(unused)              0       0     0   5     FB1_8   21    I/O     
(unused)              0       0     0   5     FB1_9   22    I/O     
(unused)              0       0     0   5     FB1_10  31    I/O     
(unused)              0       0     0   5     FB1_11  24    I/O     
(unused)              0       0     0   5     FB1_12  26    I/O     
(unused)              0       0     0   5     FB1_13        (b)     
(unused)              0       0     0   5     FB1_14  27    I/O     
(unused)              0       0     0   5     FB1_15  28    I/O     
(unused)              0       0     0   5     FB1_16  35    I/O     
div_counter<3>        5       0     0   0     FB1_17  30    GCK/I/O (b)
state<4>              8       3<-   0   0     FB1_18        (b)     (b)

Signals Used by Logic in Function Block
  1: Msub__n0029__n0005   8: counter<5>        15: state<0> 
  2: Reset                9: counter<6>        16: state<2> 
  3: clk_int             10: div_counter<0>    17: state<3> 
  4: counter<1>          11: div_counter<1>    18: state<4> 
  5: counter<2>          12: div_counter<2>    19: state<5> 
  6: counter<3>          13: div_counter<3>    20: state<7> 
  7: counter<4>          14: flag              21: state<9> 

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
div_counter<3>       .XX......XXXXXXXXXXXX................... 14
state<4>             XXXXXXXXXXXXXXXXXXXXX................... 21
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               21/33
Number of signals used by logic mapping into function block:  21
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
clkdiv                2       0     0   3     FB2_1   142   I/O     (b)
clkcnt<9>             3       0     0   2     FB2_2   143   GSR/I/O (b)
clkcnt<8>             3       0     0   2     FB2_3         (b)     (b)
clkcnt<7>             3       0     0   2     FB2_4   4     I/O     (b)
clkcnt<5>             3       0     0   2     FB2_5   2     GTS/I/O (b)
clkcnt<4>             3       0     0   2     FB2_6   3     GTS/I/O (b)
clkcnt<3>             3       0     0   2     FB2_7         (b)     (b)
clkcnt<14>            3       0     0   2     FB2_8   5     GTS/I/O (b)
clkcnt<13>            3       0     0   2     FB2_9   6     GTS/I/O (b)
clkcnt<0>             3       0     0   2     FB2_10  7     I/O     (b)
clkcnt<6>             4       0     0   1     FB2_11  9     I/O     (b)
clkcnt<18>            4       0     0   1     FB2_12  10    I/O     (b)
clkcnt<17>            4       0     0   1     FB2_13  12    I/O     (b)
clkcnt<16>            4       0     0   1     FB2_14  11    I/O     (b)
clkcnt<15>            4       0     0   1     FB2_15  13    I/O     (b)