lcd.syr

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

#      GND                         : 1
#      INV                         : 7
#      LUT1                        : 8
#      LUT1_L                      : 5
#      LUT2                        : 15
#      LUT2_D                      : 1
#      LUT2_L                      : 1
#      LUT3                        : 8
#      LUT3_D                      : 1
#      LUT3_L                      : 4
#      LUT4                        : 53
#      LUT4_D                      : 6
#      LUT4_L                      : 25
#      MUXCY                       : 30
#      MUXF5                       : 8
#      VCC                         : 1
#      XORCY                       : 31
# FlipFlops/Latches                : 42
#      FDC                         : 16
#      FDC_1                       : 1
#      FDCE                        : 5
#      FDCPE                       : 19
#      FDP                         : 1
# Clock Buffers                    : 2
#      BUFG                        : 1
#      BUFGP                       : 1
# IO Buffers                       : 12
#      IBUF                        : 1
#      OBUF                        : 3
#      OBUFT                       : 8
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-5 

 Number of Slices:                      71  out of    768     9%  
 Number of Slice Flip Flops:            42  out of   1536     2%  
 Number of 4 input LUTs:               127  out of   1536     8%  
 Number of bonded IOBs:                 13  out of     96    13%  
 Number of GCLKs:                        2  out of      4    50%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 19    |
clk_int:Q                          | BUFG                   | 20    |
tc_clkcnt(_n002085:O)              | NONE(*)(clkdiv)        | 1     |
clkdiv:Q                           | NONE                   | 2     |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 10.900ns (Maximum Frequency: 91.743MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 29.365ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 10.728ns (frequency: 93.214MHz)
  Total number of paths / destination ports: 2268 / 19
-------------------------------------------------------------------------
Delay:               10.728ns (Levels of Logic = 16)
  Source:            clkcnt_11 (FF)
  Destination:       clkcnt_18 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: clkcnt_11 to clkcnt_18
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q            2   1.292   1.340  clkcnt_11 (clkcnt_11)
     LUT4_D:I0->O          4   0.653   1.600  _n00207 (CHOICE69)
     LUT2:I1->O            7   0.653   1.950  _n002085_SW14 (N359)
     LUT4_L:I2->LO         1   0.653   0.000  clkcnt_inst_lut3_61 (clkcnt_inst_lut3_6)
     MUXCY:S->O            1   0.784   0.000  clkcnt_inst_cy_7 (clkcnt_inst_cy_7)
     MUXCY:CI->O           1   0.050   0.000  clkcnt_inst_cy_8 (clkcnt_inst_cy_8)
     MUXCY:CI->O           1   0.050   0.000  clkcnt_inst_cy_9 (clkcnt_inst_cy_9)
     MUXCY:CI->O           1   0.050   0.000  clkcnt_inst_cy_10 (clkcnt_inst_cy_10)
     MUXCY:CI->O           1   0.050   0.000  clkcnt_inst_cy_11 (clkcnt_inst_cy_11)
     MUXCY:CI->O           1   0.050   0.000  clkcnt_inst_cy_12 (clkcnt_inst_cy_12)
     MUXCY:CI->O           1   0.050   0.000  clkcnt_inst_cy_13 (clkcnt_inst_cy_13)
     MUXCY:CI->O           1   0.050   0.000  clkcnt_inst_cy_14 (clkcnt_inst_cy_14)
     MUXCY:CI->O           1   0.050   0.000  clkcnt_inst_cy_15 (clkcnt_inst_cy_15)
     MUXCY:CI->O           1   0.050   0.000  clkcnt_inst_cy_16 (clkcnt_inst_cy_16)
     MUXCY:CI->O           1   0.050   0.000  clkcnt_inst_cy_17 (clkcnt_inst_cy_17)
     MUXCY:CI->O           0   0.050   0.000  clkcnt_inst_cy_18 (clkcnt_inst_cy_18)
     XORCY:CI->O           1   0.500   0.000  clkcnt_inst_sum_18 (clkcnt_inst_sum_18)
     FDCPE:D                   0.753          clkcnt_18
    ----------------------------------------
    Total                     10.728ns (5.838ns logic, 4.890ns route)
                                       (54.4% logic, 45.6% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk_int:Q'
  Clock period: 10.900ns (frequency: 91.743MHz)
  Total number of paths / destination ports: 318 / 24
-------------------------------------------------------------------------
Delay:               10.900ns (Levels of Logic = 5)
  Source:            counter_2 (FF)
  Destination:       counter_6 (FF)
  Source Clock:      clk_int:Q rising
  Destination Clock: clk_int:Q rising

  Data Path: counter_2 to counter_6
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              8   1.292   2.050  counter_2 (counter_2)
     LUT2_L:I0->LO         1   0.653   0.100  Ker20_SW0 (N127)
     LUT4:I3->O            5   0.653   1.740  Ker20 (N20)
     LUT3_L:I0->LO         1   0.653   0.100  Ker014_SW0 (N371)
     LUT4:I2->O            4   0.653   1.600  Ker031 (N01)
     LUT4_L:I1->LO         1   0.653   0.000  _n0022<2>1 (_n0022<2>)
     FDC:D                     0.753          counter_2
    ----------------------------------------
    Total                     10.900ns (5.310ns logic, 5.590ns route)
                                       (48.7% logic, 51.3% route)

=========================================================================
Timing constraint: Default period analysis for Clock '_n002085:O'
  Clock period: 5.328ns (frequency: 187.688MHz)
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay:               5.328ns (Levels of Logic = 1)
  Source:            clkdiv (FF)
  Destination:       clkdiv (FF)
  Source Clock:      _n002085:O rising
  Destination Clock: _n002085:O rising

  Data Path: clkdiv to clkdiv
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              3   1.292   1.480  clkdiv (clkdiv)
     INV:I->O              1   0.653   1.150  _n00561_INV_0 (_n0056)
     FDC:D                     0.753          clkdiv
    ----------------------------------------
    Total                      5.328ns (2.698ns logic, 2.630ns route)
                                       (50.6% logic, 49.4% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'clkdiv:Q'
  Clock period: 9.021ns (frequency: 110.852MHz)
  Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Delay:               9.021ns (Levels of Logic = 2)
  Source:            clk_int (FF)
  Destination:       clk_int (FF)
  Source Clock:      clkdiv:Q rising
  Destination Clock: clkdiv:Q rising

  Data Path: clk_int to clk_int
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              1   1.292   1.150  clk_int (clk_int1)
     BUFG:I->O            21   0.773   3.250  clk_int_BUFG (clk_int)
     INV:I->O              1   0.653   1.150  _n00571_INV_0 (_n0057)
     FDC:D                     0.753          clk_int
    ----------------------------------------
    Total                      9.021ns (3.471ns logic, 5.550ns route)
                                       (38.5% logic, 61.5% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clkdiv:Q'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              8.189ns (Levels of Logic = 1)
  Source:            lcd_e (FF)
  Destination:       lcd_e (PAD)
  Source Clock:      clkdiv:Q falling

  Data Path: lcd_e to lcd_e
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q            2   1.292   1.340  lcd_e (lcd_e_OBUF)
     OBUF:I->O                 5.557          lcd_e_OBUF (lcd_e)
    ----------------------------------------
    Total                      8.189ns (6.849ns logic, 1.340ns route)
                                       (83.6% logic, 16.4% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk_int:Q'
  Total number of paths / destination ports: 3386 / 10
-------------------------------------------------------------------------
Offset:              29.365ns (Levels of Logic = 13)
  Source:            counter_3 (FF)
  Destination:       data<5> (PAD)
  Source Clock:      clk_int:Q rising

  Data Path: counter_3 to data<5>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             13   1.292   2.500  counter_3 (counter_3)
     LUT4:I0->O            1   0.653   1.150  _n003854_SW0 (N383)
     LUT4:I3->O            5   0.653   1.740  _n003854 (CHOICE27)
     LUT3:I2->O            1   0.653   0.000  lcd__n0028<3>lut (N9)
     MUXCY:S->O            1   0.784   0.000  lcd__n0028<3>cy (lcd__n0028<3>_cyo)
     XORCY:CI->O           2   0.500   1.340  lcd__n0028<4>_xor (_n0028<4>)
     LUT4:I2->O            1   0.653   1.150  char_addr<4>_SW1 (N381)
     LUT4:I2->O           13   0.653   2.500  char_addr<4> (char_addr<4>)
     LUT4:I2->O            1   0.653   0.000  aa/Mrom__n0000_inst_mux_f5_5111_F (N397)
     MUXF5:I0->O           1   0.375   1.150  aa/Mrom__n0000_inst_mux_f5_5111 (aa/_n0000<5>)
     LUT2:I0->O            1   0.653   1.150  aa/data<5>1 (data_in<5>)
     LUT4:I0->O            1   0.653   1.150  _n0033<5>1 (N25)
     LUT4:I3->O            1   0.653   1.150  _n0033<5>2 (data_5_OBUFT)
     OBUFT:I->O                5.557          data_5_OBUFT (data<5>)
    ----------------------------------------
    Total                     29.365ns (14.385ns logic, 14.980ns route)
                                       (49.0% logic, 51.0% route)

=========================================================================
CPU : 14.49 / 15.17 s | Elapsed : 15.00 / 15.00 s
 
--> 

Total memory usage is 76804 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    3 (   0 filtered)
Number of infos    :    3 (   0 filtered)