ps2.syr

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

Release 7.1.04i - xst H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
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--> Reading design: ps2.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "ps2.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "ps2"
Output Format                      : NGC
Target Device                      : xc2s50-6-tq144

---- Source Options
Top Module Name                    : ps2
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : ps2.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
tristate2logic                     : Yes
use_clock_enable                   : No
use_sync_set                       : No
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "E:/temp/SPARTAN2/vhdl/Interface/ps2/ps2.vhd" in Library work.
Entity <ps2> compiled.
Entity <ps2> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <ps2> (Architecture <behavioral>).
WARNING:Xst:819 - "E:/temp/SPARTAN2/vhdl/Interface/ps2/ps2.vhd" line 117: The following signals are missing in the process sensitivity list:
   parbit.
Entity <ps2> analyzed. Unit <ps2> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <ps2>.
    Related source file is "E:/temp/SPARTAN2/vhdl/Interface/ps2/ps2.vhd".
    Found finite state machine <FSM_0> for signal <c_state>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 10                                             |
    | Inputs             | 3                                              |
    | Outputs            | 4                                              |
    | Clock              | clock (rising_edge)                            |
    | Reset              | resetn (negative)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 8-bit register for signal <leds>.
    Found 8-bit 4-to-1 multiplexer for signal <$n0011>.
    Found 3-bit adder for signal <$n0014> created at line 79.
    Found 1-bit xor2 for signal <$n0019> created at line 147.
    Found 1-bit register for signal <act_ps2_clk>.
    Found 3-bit register for signal <cntval>.
    Found 1-bit register for signal <err>.
    Found 1-bit register for signal <latch>.
    Found 1-bit register for signal <parbit>.
    Found 1-bit register for signal <parset>.
    Found 1-bit register for signal <prv_ps2_clk>.
    Found 8-bit register for signal <recdata>.
    Found 1-bit register for signal <shift>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  26 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
	inferred   8 Multiplexer(s).
Unit <ps2> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <c_state[1:2]> with sequential encoding.
--------------------
 State  | Encoding
--------------------
 idle   | 00
 start  | 01
 data   | 10
 parity | 11
--------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# Adders/Subtractors               : 1
 3-bit adder                       : 1
# Registers                        : 12
 1-bit register                    : 9
 3-bit register                    : 1
 8-bit register                    : 2
# Multiplexers                     : 1
 8-bit 4-to-1 multiplexer          : 1
# Xors                             : 1
 1-bit xor2                        : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <ps2> ...
Loading device for application Rf_Device from file 'v50.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block ps2, actual ratio is 2.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : ps2.ngr
Top Level Output File Name         : ps2
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 12

Macro Statistics :
# Registers                        : 10
#      1-bit register              : 7
#      3-bit register              : 1
#      8-bit register              : 2
# Multiplexers                     : 1
#      8-bit 4-to-1 multiplexer    : 1

Cell Usage :
# BELS                             : 35
#      INV                         : 1
#      LUT2                        : 1
#      LUT2_L                      : 3
#      LUT3                        : 2
#      LUT3_L                      : 11
#      LUT4_L                      : 16
#      MUXF5                       : 1
# FlipFlops/Latches                : 28
#      FDC                         : 16
#      FDP                         : 12
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 11
#      IBUF                        : 3
#      OBUF                        : 8
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-6 

 Number of Slices:                      18  out of    768     2%  
 Number of Slice Flip Flops:            28  out of   1536     1%  
 Number of 4 input LUTs:                33  out of   1536     2%  
 Number of bonded IOBs:                 12  out of     96    12%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clock                              | BUFGP                  | 28    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 5.969ns (Maximum Frequency: 167.532MHz)
   Minimum input arrival time before clock: 5.283ns
   Maximum output required time after clock: 6.959ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clock'
  Clock period: 5.969ns (frequency: 167.532MHz)
  Total number of paths / destination ports: 105 / 27
-------------------------------------------------------------------------
Delay:               5.969ns (Levels of Logic = 3)
  Source:            cntval_0 (FF)
  Destination:       c_state_FFd2 (FF)
  Source Clock:      clock rising
  Destination Clock: clock rising

  Data Path: cntval_0 to c_state_FFd2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              4   1.085   1.440  cntval_0 (cntval_0)
     LUT3:I2->O            3   0.549   1.332  _n00181 (_n0018)
     LUT4_L:I3->LO         1   0.549   0.000  c_state_FFd2-In1_G (N58)
     MUXF5:I1->O           1   0.305   0.000  c_state_FFd2-In1 (c_state_FFd2-In)
     FDC:D                     0.709          c_state_FFd2
    ----------------------------------------
    Total                      5.969ns (3.197ns logic, 2.772ns route)
                                       (53.6% logic, 46.4% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clock'
  Total number of paths / destination ports: 7 / 6
-------------------------------------------------------------------------
Offset:              5.283ns (Levels of Logic = 3)
  Source:            ps2_dta (PAD)
  Destination:       err (FF)
  Destination Clock: clock rising

  Data Path: ps2_dta to err
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             6   0.776   1.665  ps2_dta_IBUF (ps2_dta_IBUF)
     LUT2:I1->O            1   0.549   1.035  n_err2 (CHOICE81)
     LUT4_L:I0->LO         1   0.549   0.000  n_err51 (n_err)
     FDC:D                     0.709          err
    ----------------------------------------
    Total                      5.283ns (2.583ns logic, 2.700ns route)
                                       (48.9% logic, 51.1% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clock'
  Total number of paths / destination ports: 8 / 8
-------------------------------------------------------------------------
Offset:              6.959ns (Levels of Logic = 1)
  Source:            leds_7 (FF)
  Destination:       leds<7> (PAD)
  Source Clock:      clock rising

  Data Path: leds_7 to leds<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDP:C->Q              2   1.085   1.206  leds_7 (leds_7)
     OBUF:I->O                 4.668          leds_7_OBUF (leds<7>)
    ----------------------------------------
    Total                      6.959ns (5.753ns logic, 1.206ns route)
                                       (82.7% logic, 17.3% route)

=========================================================================
CPU : 6.95 / 9.68 s | Elapsed : 7.00 / 9.00 s
 
--> 

Total memory usage is 75780 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    1 (   0 filtered)
Number of infos    :    0 (   0 filtered)