📄 ps2.rpt
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cpldfit: version H.42 Xilinx Inc.
Fitter Report
Design Name: ps2 Date: 2-21-2006, 11:09AM
Device Used: XC95144XL-10-TQ144
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
35 /144 ( 24%) 59 /720 ( 8%) 49 /432 ( 11%) 20 /144 ( 14%) 25 /117 ( 21%)
** Function Block Resources **
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 3/18 4/54 6/90 0/15
FB2 3/18 4/54 6/90 0/15
FB3 8/18 9/54 16/90 8/15
FB4 6/18 8/54 2/90 6/15
FB5 3/18 4/54 6/90 0/14
FB6 8/18 8/54 16/90 8/13
FB7 3/18 4/54 6/90 0/15
FB8 1/18 8/54 1/90 1/15
----- ----- ----- -----
35/144 49/432 59/720 23/117
* - Resource is exhausted
** Global Control Resources **
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 2 2 | I/O : 25 109
Output : 23 23 | GCK/IO : 0 3
Bidirectional : 0 0 | GTS/IO : 0 4
GCK : 0 0 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 25 25
** Power Data **
There are 35 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
************************* Summary of Mapped Logic ************************
** 23 Outputs **
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
led<5> 2 2 FB3_5 33 I/O O STD FAST SET
led<4> 2 2 FB3_9 40 I/O O STD FAST SET
led<7> 2 2 FB3_10 48 I/O O STD FAST SET
led<3> 2 2 FB3_11 43 I/O O STD FAST SET
led<2> 2 2 FB3_12 45 I/O O STD FAST SET
led<1> 2 2 FB3_14 49 I/O O STD FAST SET
led<6> 2 2 FB3_15 50 I/O O STD FAST SET
led<0> 2 2 FB3_17 51 I/O O STD FAST SET
dataout<6> 2 8 FB4_1 118 I/O O STD FAST
en<2> 0 0 FB4_2 126 I/O O STD FAST
en<6> 0 0 FB4_3 133 I/O O STD FAST
en<0> 0 0 FB4_9 131 I/O O STD FAST
en<1> 0 0 FB4_11 132 I/O O STD FAST
en<7> 0 0 FB4_12 134 I/O O STD FAST
dataout<0> 3 8 FB6_2 106 I/O O STD FAST
dataout<2> 5 8 FB6_4 111 I/O O STD FAST
dataout<3> 3 8 FB6_8 113 I/O O STD FAST
dataout<5> 3 8 FB6_9 116 I/O O STD FAST
dataout<4> 2 8 FB6_10 115 I/O O STD FAST
en<3> 0 0 FB6_12 120 I/O O STD FAST
en<4> 0 0 FB6_15 124 I/O O STD FAST
en<5> 0 0 FB6_17 125 I/O O STD FAST
dataout<1> 1 8 FB8_16 107 I/O O STD FAST
** 12 Buried Nodes **
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
master<2> 2 2 FB1_16 STD RESET
master<1> 2 2 FB1_17 STD RESET
master<0> 2 2 FB1_18 STD RESET
master<5> 2 2 FB2_16 STD RESET
master<4> 2 2 FB2_17 STD RESET
master<3> 2 2 FB2_18 STD RESET
master<8> 2 2 FB5_16 STD RESET
master<7> 2 2 FB5_17 STD RESET
master<6> 2 2 FB5_18 STD RESET
slave<9> 2 2 FB7_16 STD RESET
slave<8> 2 2 FB7_17 STD RESET
master<9> 2 2 FB7_18 STD RESET
** 2 Inputs **
Signal Loc Pin Pin Pin
Name No. Type Use
kb_clk FB7_15 87 I/O I
kb_data FB7_17 88 I/O I
Legend:
Pin No. - ~ - User Assigned
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X - Signal used as input to the macrocell logic.
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 4/50
Number of signals used by logic mapping into function block: 4
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB1_1 23 I/O
(unused) 0 0 0 5 FB1_2 16 I/O
(unused) 0 0 0 5 FB1_3 17 I/O
(unused) 0 0 0 5 FB1_4 25 I/O
(unused) 0 0 0 5 FB1_5 19 I/O
(unused) 0 0 0 5 FB1_6 20 I/O
(unused) 0 0 0 5 FB1_7 (b)
(unused) 0 0 0 5 FB1_8 21 I/O
(unused) 0 0 0 5 FB1_9 22 I/O
(unused) 0 0 0 5 FB1_10 31 I/O
(unused) 0 0 0 5 FB1_11 24 I/O
(unused) 0 0 0 5 FB1_12 26 I/O
(unused) 0 0 0 5 FB1_13 (b)
(unused) 0 0 0 5 FB1_14 27 I/O
(unused) 0 0 0 5 FB1_15 28 I/O
master<2> 2 0 0 3 FB1_16 35 I/O (b)
master<1> 2 0 0 3 FB1_17 30 GCK/I/O (b)
master<0> 2 0 0 3 FB1_18 (b) (b)
Signals Used by Logic in Function Block
1: kb_clk 3: led<2> 4: led<3>
2: led<1>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
master<2> X..X.................................... 2
master<1> X.X..................................... 2
master<0> XX...................................... 2
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 4/50
Number of signals used by logic mapping into function block: 4
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB2_1 142 I/O
(unused) 0 0 0 5 FB2_2 143 GSR/I/O
(unused) 0 0 0 5 FB2_3 (b)
(unused) 0 0 0 5 FB2_4 4 I/O
(unused) 0 0 0 5 FB2_5 2 GTS/I/O
(unused) 0 0 0 5 FB2_6 3 GTS/I/O
(unused) 0 0 0 5 FB2_7 (b)
(unused) 0 0 0 5 FB2_8 5 GTS/I/O
(unused) 0 0 0 5 FB2_9 6 GTS/I/O
(unused) 0 0 0 5 FB2_10 7 I/O
(unused) 0 0 0 5 FB2_11 9 I/O
(unused) 0 0 0 5 FB2_12 10 I/O
(unused) 0 0 0 5 FB2_13 12 I/O
(unused) 0 0 0 5 FB2_14 11 I/O
(unused) 0 0 0 5 FB2_15 13 I/O
master<5> 2 0 0 3 FB2_16 14 I/O (b)
master<4> 2 0 0 3 FB2_17 15 I/O (b)
master<3> 2 0 0 3 FB2_18 (b) (b)
Signals Used by Logic in Function Block
1: kb_clk 3: led<5> 4: led<6>
2: led<4>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
master<5> X..X.................................... 2
master<4> X.X..................................... 2
master<3> XX...................................... 2
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 9/45
Number of signals used by logic mapping into function block: 9
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB3_1 39 I/O
(unused) 0 0 0 5 FB3_2 32 GCK/I/O
(unused) 0 0 0 5 FB3_3 41 I/O
(unused) 0 0 0 5 FB3_4 44 I/O
led<5> 2 0 0 3 FB3_5 33 I/O O
(unused) 0 0 0 5 FB3_6 34 I/O
(unused) 0 0 0 5 FB3_7 46 I/O
(unused) 0 0 0 5 FB3_8 38 GCK/I/O
led<4> 2 0 0 3 FB3_9 40 I/O O
led<7> 2 0 0 3 FB3_10 48 I/O O
led<3> 2 0 0 3 FB3_11 43 I/O O
led<2> 2 0 0 3 FB3_12 45 I/O O
(unused) 0 0 0 5 FB3_13 (b)
led<1> 2 0 0 3 FB3_14 49 I/O O
led<6> 2 0 0 3 FB3_15 50 I/O O
(unused) 0 0 0 5 FB3_16 (b)
led<0> 2 0 0 3 FB3_17 51 I/O O
(unused) 0 0 0 5 FB3_18 (b)
Signals Used by Logic in Function Block
1: kb_clk 4: master<2> 7: master<5>
2: master<0> 5: master<3> 8: master<6>
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