ps2.twr

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

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Release 7.1i Trace H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

D:/Xilinx/bin/nt/trce.exe -ise e:\temp\spartan2\vhdl\interface\ps2\ps2.ise
-intstyle ise -e 3 -l 3 -s 6 -xml ps2 ps2.ncd -o ps2.twr ps2.pcf


Design file:              ps2.ncd
Physical constraint file: ps2.pcf
Device,speed:             xc2s50,-6 (PRODUCTION 1.27 2005-01-22)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clock
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
ps2_clk     |    0.719(R)|   -0.151(R)|clock_BUFGP       |   0.000|
ps2_dta     |    3.740(R)|   -1.518(R)|clock_BUFGP       |   0.000|
------------+------------+------------+------------------+--------+

Clock clock to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
leds<0>     |    8.796(R)|clock_BUFGP       |   0.000|
leds<1>     |    9.100(R)|clock_BUFGP       |   0.000|
leds<2>     |    9.107(R)|clock_BUFGP       |   0.000|
leds<3>     |    9.164(R)|clock_BUFGP       |   0.000|
leds<4>     |    9.473(R)|clock_BUFGP       |   0.000|
leds<5>     |    9.964(R)|clock_BUFGP       |   0.000|
leds<6>     |    9.389(R)|clock_BUFGP       |   0.000|
leds<7>     |    9.459(R)|clock_BUFGP       |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clock
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clock          |    5.734|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Tue Mar 14 15:06:08 2006
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Peak Memory Usage: 62 MB