📄 seg73.mfd
字号:
cntthird<2>.AR = !rst;
MACROCELL | 3 | 16 | cntfirst<3>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 18 | 3 | 9 | 3 | 10 | 3 | 16 | 3 | 0 | 3 | 3 | 5 | 9 | 3 | 13 | 5 | 2 | 7 | 15 | 3 | 4 | 3 | 1 | 3 | 5 | 3 | 7 | 3 | 8 | 5 | 4 | 5 | 8 | 7 | 16 | 7 | 17
INPUTS | 7 | cntfirst<0> | cntfirst<1> | cntfirst<2> | last_over | cntfirst<3> | div_cnt<24> | rst
INPUTMC | 6 | 7 | 7 | 3 | 11 | 7 | 0 | 7 | 11 | 3 | 16 | 0 | 3
INPUTP | 1 | 79
EQ | 7 |
cntfirst<3>.T = cntfirst<3> & last_over
# cntfirst<0> & cntfirst<1> & cntfirst<2> &
!last_over
# cntfirst<0> & !cntfirst<1> & !cntfirst<2> &
cntfirst<3>;
cntfirst<3>.CLK = div_cnt<24>;
cntfirst<3>.AR = !rst;
MACROCELL | 7 | 2 | cntlast<3>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 18 | 7 | 1 | 7 | 2 | 7 | 11 | 3 | 0 | 3 | 3 | 5 | 9 | 3 | 13 | 5 | 3 | 7 | 15 | 3 | 4 | 3 | 2 | 3 | 6 | 3 | 12 | 3 | 17 | 5 | 4 | 5 | 8 | 7 | 14 | 7 | 17
INPUTS | 6 | cntlast<0> | cntlast<1> | cntlast<2> | cntlast<3> | third_over | rst
INPUTMC | 5 | 7 | 14 | 7 | 1 | 7 | 8 | 7 | 2 | 7 | 13
INPUTP | 1 | 79
EQ | 5 |
cntlast<3>.T = cntlast<0> & cntlast<1> & cntlast<2>
# cntlast<0> & !cntlast<1> & !cntlast<2> &
cntlast<3>;
cntlast<3>.CLK = third_over;
cntlast<3>.AR = !rst;
MACROCELL | 7 | 4 | cntsecond<3>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 16 | 7 | 12 | 7 | 3 | 7 | 4 | 3 | 0 | 3 | 3 | 5 | 9 | 3 | 12 | 5 | 3 | 7 | 15 | 3 | 5 | 3 | 2 | 3 | 4 | 3 | 17 | 5 | 2 | 7 | 14 | 7 | 16
INPUTS | 6 | cntsecond<0> | cntsecond<1> | cntsecond<2> | cntsecond<3> | first_over | rst
INPUTMC | 5 | 7 | 17 | 7 | 3 | 7 | 9 | 7 | 4 | 3 | 9
INPUTP | 1 | 79
EQ | 5 |
cntsecond<3>.T = cntsecond<0> & cntsecond<1> & cntsecond<2>
# cntsecond<0> & !cntsecond<1> & !cntsecond<2> &
cntsecond<3>;
cntsecond<3>.CLK = first_over;
cntsecond<3>.AR = !rst;
MACROCELL | 7 | 6 | cntthird<3>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 19 | 7 | 13 | 7 | 5 | 7 | 6 | 3 | 0 | 3 | 3 | 5 | 9 | 3 | 13 | 5 | 3 | 7 | 15 | 3 | 4 | 3 | 2 | 3 | 6 | 3 | 7 | 3 | 17 | 5 | 2 | 5 | 4 | 5 | 8 | 7 | 16 | 7 | 17
INPUTS | 6 | cntthird<0> | cntthird<1> | cntthird<2> | cntthird<3> | second_over | rst
INPUTMC | 5 | 1 | 11 | 7 | 5 | 7 | 10 | 7 | 6 | 7 | 12
INPUTP | 1 | 79
EQ | 5 |
cntthird<3>.T = cntthird<0> & cntthird<1> & cntthird<2>
# cntthird<0> & !cntthird<1> & !cntthird<2> &
cntthird<3>;
cntthird<3>.CLK = second_over;
cntthird<3>.AR = !rst;
MACROCELL | 1 | 10 | div_cnt<0>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 24 | 0 | 9 | 0 | 8 | 0 | 3 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 1 | 17 | 0 | 7 | 0 | 6 | 0 | 5 | 0 | 4 | 1 | 16 | 1 | 15 | 1 | 14 | 1 | 13 | 1 | 12 | 0 | 2 | 0 | 1 | 0 | 0
INPUTS | 2 | clk | rst
INPUTP | 2 | 143 | 79
EQ | 3 |
div_cnt<0>.T = Vcc;
div_cnt<0>.CLK = clk;
div_cnt<0>.AR = !rst;
MACROCELL | 0 | 17 | div_cnt<10>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 14 | 0 | 9 | 0 | 8 | 0 | 3 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 7 | 0 | 6 | 0 | 5 | 0 | 4
INPUTS | 12 | div_cnt<0> | div_cnt<1> | div_cnt<2> | div_cnt<3> | div_cnt<4> | div_cnt<5> | div_cnt<6> | div_cnt<7> | div_cnt<8> | div_cnt<9> | clk | rst
INPUTMC | 10 | 1 | 10 | 1 | 17 | 1 | 16 | 1 | 15 | 1 | 14 | 1 | 13 | 1 | 12 | 0 | 2 | 0 | 1 | 0 | 0
INPUTP | 2 | 143 | 79
EQ | 5 |
div_cnt<10>.T = div_cnt<0> & div_cnt<1> & div_cnt<2> &
div_cnt<3> & div_cnt<4> & div_cnt<5> & div_cnt<6> &
div_cnt<7> & div_cnt<8> & div_cnt<9>;
div_cnt<10>.CLK = clk;
div_cnt<10>.AR = !rst;
MACROCELL | 0 | 16 | div_cnt<11>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 13 | 0 | 9 | 0 | 8 | 0 | 3 | 0 | 15 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 7 | 0 | 6 | 0 | 5 | 0 | 4
INPUTS | 13 | div_cnt<0> | div_cnt<10> | div_cnt<1> | div_cnt<2> | div_cnt<3> | div_cnt<4> | div_cnt<5> | div_cnt<6> | div_cnt<7> | div_cnt<8> | div_cnt<9> | clk | rst
INPUTMC | 11 | 1 | 10 | 0 | 17 | 1 | 17 | 1 | 16 | 1 | 15 | 1 | 14 | 1 | 13 | 1 | 12 | 0 | 2 | 0 | 1 | 0 | 0
INPUTP | 2 | 143 | 79
EQ | 5 |
div_cnt<11>.T = div_cnt<0> & div_cnt<10> & div_cnt<1> &
div_cnt<2> & div_cnt<3> & div_cnt<4> & div_cnt<5> &
div_cnt<6> & div_cnt<7> & div_cnt<8> & div_cnt<9>;
div_cnt<11>.CLK = clk;
div_cnt<11>.AR = !rst;
MACROCELL | 0 | 15 | div_cnt<12>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 12 | 0 | 9 | 0 | 8 | 0 | 3 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 7 | 0 | 6 | 0 | 5 | 0 | 4
INPUTS | 14 | div_cnt<0> | div_cnt<10> | div_cnt<11> | div_cnt<1> | div_cnt<2> | div_cnt<3> | div_cnt<4> | div_cnt<5> | div_cnt<6> | div_cnt<7> | div_cnt<8> | div_cnt<9> | clk | rst
INPUTMC | 12 | 1 | 10 | 0 | 17 | 0 | 16 | 1 | 17 | 1 | 16 | 1 | 15 | 1 | 14 | 1 | 13 | 1 | 12 | 0 | 2 | 0 | 1 | 0 | 0
INPUTP | 2 | 143 | 79
EQ | 6 |
div_cnt<12>.T = div_cnt<0> & div_cnt<10> & div_cnt<11> &
div_cnt<1> & div_cnt<2> & div_cnt<3> & div_cnt<4> &
div_cnt<5> & div_cnt<6> & div_cnt<7> & div_cnt<8> &
div_cnt<9>;
div_cnt<12>.CLK = clk;
div_cnt<12>.AR = !rst;
MACROCELL | 0 | 14 | div_cnt<13>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 11 | 0 | 9 | 0 | 8 | 0 | 3 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 7 | 0 | 6 | 0 | 5 | 0 | 4
INPUTS | 15 | div_cnt<0> | div_cnt<10> | div_cnt<11> | div_cnt<12> | div_cnt<1> | div_cnt<2> | div_cnt<3> | div_cnt<4> | div_cnt<5> | div_cnt<6> | div_cnt<7> | div_cnt<8> | div_cnt<9> | clk | rst
INPUTMC | 13 | 1 | 10 | 0 | 17 | 0 | 16 | 0 | 15 | 1 | 17 | 1 | 16 | 1 | 15 | 1 | 14 | 1 | 13 | 1 | 12 | 0 | 2 | 0 | 1 | 0 | 0
INPUTP | 2 | 143 | 79
EQ | 6 |
div_cnt<13>.T = div_cnt<0> & div_cnt<10> & div_cnt<11> &
div_cnt<12> & div_cnt<1> & div_cnt<2> & div_cnt<3> &
div_cnt<4> & div_cnt<5> & div_cnt<6> & div_cnt<7> &
div_cnt<8> & div_cnt<9>;
div_cnt<13>.CLK = clk;
div_cnt<13>.AR = !rst;
MACROCELL | 0 | 13 | div_cnt<14>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 10 | 0 | 9 | 0 | 8 | 0 | 3 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 7 | 0 | 6 | 0 | 5 | 0 | 4
INPUTS | 16 | div_cnt<0> | div_cnt<10> | div_cnt<11> | div_cnt<12> | div_cnt<13> | div_cnt<1> | div_cnt<2> | div_cnt<3> | div_cnt<4> | div_cnt<5> | div_cnt<6> | div_cnt<7> | div_cnt<8> | div_cnt<9> | clk | rst
INPUTMC | 14 | 1 | 10 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 1 | 17 | 1 | 16 | 1 | 15 | 1 | 14 | 1 | 13 | 1 | 12 | 0 | 2 | 0 | 1 | 0 | 0
INPUTP | 2 | 143 | 79
EQ | 6 |
div_cnt<14>.T = div_cnt<0> & div_cnt<10> & div_cnt<11> &
div_cnt<12> & div_cnt<13> & div_cnt<1> & div_cnt<2> &
div_cnt<3> & div_cnt<4> & div_cnt<5> & div_cnt<6> &
div_cnt<7> & div_cnt<8> & div_cnt<9>;
div_cnt<14>.CLK = clk;
div_cnt<14>.AR = !rst;
MACROCELL | 0 | 12 | div_cnt<15>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 9 | 0 | 9 | 0 | 8 | 0 | 3 | 0 | 11 | 0 | 10 | 0 | 7 | 0 | 6 | 0 | 5 | 0 | 4
INPUTS | 17 | div_cnt<0> | div_cnt<10> | div_cnt<11> | div_cnt<12> | div_cnt<13> | div_cnt<14> | div_cnt<1> | div_cnt<2> | div_cnt<3> | div_cnt<4> | div_cnt<5> | div_cnt<6> | div_cnt<7> | div_cnt<8> | div_cnt<9> | clk | rst
INPUTMC | 15 | 1 | 10 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 13 | 1 | 17 | 1 | 16 | 1 | 15 | 1 | 14 | 1 | 13 | 1 | 12 | 0 | 2 | 0 | 1 | 0 | 0
INPUTP | 2 | 143 | 79
EQ | 6 |
div_cnt<15>.T = div_cnt<0> & div_cnt<10> & div_cnt<11> &
div_cnt<12> & div_cnt<13> & div_cnt<14> & div_cnt<1> &
div_cnt<2> & div_cnt<3> & div_cnt<4> & div_cnt<5> &
div_cnt<6> & div_cnt<7> & div_cnt<8> & div_cnt<9>;
div_cnt<15>.CLK = clk;
div_cnt<15>.AR = !rst;
MACROCELL | 0 | 11 | div_cnt<16>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 8 | 0 | 9 | 0 | 8 | 0 | 3 | 0 | 10 | 0 | 7 | 0 | 6 | 0 | 5 | 0 | 4
INPUTS | 18 | div_cnt<0> | div_cnt<10> | div_cnt<11> | div_cnt<12> | div_cnt<13> | div_cnt<14> | div_cnt<15> | div_cnt<1> | div_cnt<2> | div_cnt<3> | div_cnt<4> | div_cnt<5> | div_cnt<6> | div_cnt<7> | div_cnt<8> | div_cnt<9> | clk | rst
INPUTMC | 16 | 1 | 10 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 13 | 0 | 12 | 1 | 17 | 1 | 16 | 1 | 15 | 1 | 14 | 1 | 13 | 1 | 12 | 0 | 2 | 0 | 1 | 0 | 0
INPUTP | 2 | 143 | 79
EQ | 7 |
div_cnt<16>.T = div_cnt<0> & div_cnt<10> & div_cnt<11> &
div_cnt<12> & div_cnt<13> & div_cnt<14> & div_cnt<15> &
div_cnt<1> & div_cnt<2> & div_cnt<3> & div_cnt<4> &
div_cnt<5> & div_cnt<6> & div_cnt<7> & div_cnt<8> &
div_cnt<9>;
div_cnt<16>.CLK = clk;
div_cnt<16>.AR = !rst;
MACROCELL | 0 | 10 | div_cnt<17>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 7 | 0 | 9 | 0 | 8 | 0 | 3 | 0 | 7 | 0 | 6 | 0 | 5 | 0 | 4
INPUTS | 19 | div_cnt<0> | div_cnt<10> | div_cnt<11> | div_cnt<12> | div_cnt<13> | div_cnt<14> | div_cnt<15> | div_cnt<16> | div_cnt<1> | div_cnt<2> | div_cnt<3> | div_cnt<4> | div_cnt<5> | div_cnt<6> | div_cnt<7> | div_cnt<8> | div_cnt<9> | clk | rst
INPUTMC | 17 | 1 | 10 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 1 | 17 | 1 | 16 | 1 | 15 | 1 | 14 | 1 | 13 | 1 | 12 | 0 | 2 | 0 | 1 | 0 | 0
INPUTP | 2 | 143 | 79
EQ | 7 |
div_cnt<17>.T = div_cnt<0> & div_cnt<10> & div_cnt<11> &
div_cnt<12> & div_cnt<13> & div_cnt<14> & div_cnt<15> &
div_cnt<16> & div_cnt<1> & div_cnt<2> & div_cnt<3> &
div_cnt<4> & div_cnt<5> & div_cnt<6> & div_cnt<7> &
div_cnt<8> & div_cnt<9>;
div_cnt<17>.CLK = clk;
div_cnt<17>.AR = !rst;
MACROCELL | 1 | 17 | div_cnt<1>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 23 | 0 | 9 | 0 | 8 | 0 | 3 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 7 | 0 | 6 | 0 | 5 | 0 | 4 | 1 | 16 | 1 | 15 | 1 | 14 | 1 | 13 | 1 | 12 | 0 | 2 | 0 | 1 | 0 | 0
INPUTS | 3 | div_cnt<0> | clk | rst
INPUTMC | 1 | 1 | 10
INPUTP | 2 | 143 | 79
EQ | 3 |
div_cnt<1>.T = div_cnt<0>;
div_cnt<1>.CLK = clk;
div_cnt<1>.AR = !rst;
MACROCELL | 0 | 7 | div_cnt<20>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 4 | 0 | 3 | 0 | 6 | 0 | 5 | 0 | 4
INPUTS | 22 | div_cnt<18> | div_cnt<19> | div_cnt<0> | div_cnt<10> | div_cnt<11> | div_cnt<12> | div_cnt<13> | div_cnt<14> | div_cnt<15> | div_cnt<16> | div_cnt<17> | div_cnt<1> | div_cnt<2> | div_cnt<3> | div_cnt<4> | div_cnt<5> | div_cnt<6> | div_cnt<7> | div_cnt<8> | div_cnt<9> | clk | rst
INPUTMC | 20 | 0 | 9 | 0 | 8 | 1 | 10 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 1 | 17 | 1 | 16 | 1 | 15 | 1 | 14 | 1 | 13 | 1 | 12 | 0 | 2 | 0 | 1 | 0 | 0
INPUTP | 2 | 143 | 79
EQ | 8 |
div_cnt<20>.T = div_cnt<18> & div_cnt<19> & div_cnt<0> &
div_cnt<10> & div_cnt<11> & div_cnt<12> & div_cnt<13> &
div_cnt<14> & div_cnt<15> & div_cnt<16> & div_cnt<17> &
div_cnt<1> & div_cnt<2> & div_cnt<3> & div_cnt<4> &
div_cnt<5> & div_cnt<6> & div_cnt<7> & div_cnt<8> &
div_cnt<9>;
div_cnt<20>.CLK = clk;
div_cnt<20>.AR = !rst;
MACROCELL | 0 | 6 | div_cnt<21>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 3 | 0 | 3 | 0 | 5 | 0 | 4
INPUTS | 23 | div_cnt<18> | div_cnt<19> | div_cnt<0> | div_cnt<10> | div_cnt<11> | div_cnt<12> | div_cnt<13> | div_cnt<14> | div_cnt<15> | div_cnt<16> | div_cnt<17> | div_cnt<1> | div_cnt<20> | div_cnt<2> | div_cnt<3> | div_cnt<4> | div_cnt<5> | div_cnt<6> | div_cnt<7> | div_cnt<8> | div_cnt<9> | clk | rst
INPUTMC | 21 | 0 | 9 | 0 | 8 | 1 | 10 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 1 | 17 | 0 | 7 | 1 | 16 | 1 | 15 | 1 | 14 | 1 | 13 | 1 | 12 | 0 | 2 | 0 | 1 | 0 | 0
INPUTP | 2 | 143 | 79
EQ | 8 |
div_cnt<21>.T = div_cnt<18> & div_cnt<19> & div_cnt<0> &
div_cnt<10> & div_cnt<11> & div_cnt<12> & div_cnt<13> &
div_cnt<14> & div_cnt<15> & div_cnt<16> & div_cnt<17> &
div_cnt<1> & div_cnt<20> & div_cnt<2> & div_cnt<3> &
div_cnt<4> & div_cnt<5> & div_cnt<6> & div_cnt<7> &
div_cnt<8> & div_cnt<9>;
div_cnt<21>.CLK = clk;
div_cnt<21>.AR = !rst;
MACROCELL | 0 | 5 | div_cnt<22>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 2 | 0 | 3 | 0 | 4
INPUTS | 24 | div_cnt<18> | div_cnt<19> | div_cnt<0> | div_cnt<10> | div_cnt<11> | div_cnt<12> | div_cnt<13> | div_cnt<14> | div_cnt<15> | div_cnt<16> | div_cnt<17> | div_cnt<1> | div_cnt<20> | div_cnt<21> | div_cnt<2> | div_cnt<3> | div_cnt<4> | div_cnt<5> | div_cnt<6> | div_cnt<7> | div_cnt<8> | div_cnt<9> | clk | rst
INPUTMC | 22 | 0 | 9 | 0 | 8 | 1 | 10 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 1 | 17 | 0 | 7 | 0 | 6 | 1 | 16 | 1 | 15 | 1 | 14 | 1 | 13 | 1 | 12 | 0 | 2 | 0 | 1 | 0 | 0
INPUTP | 2 | 143 | 79
EQ | 8 |
div_cnt<22>.T = div_cnt<18> & div_cnt<19> & div_cnt<0> &
div_cnt<10> & div_cnt<11> & div_cnt<12> & div_cnt<13> &
div_cnt<14> & div_cnt<15> & div_cnt<16> & div_cnt<17> &
div_cnt<1> & div_cnt<20> & div_cnt<21> & div_cnt<2> &
div_cnt<3> & div_cnt<4> & div_cnt<5> & div_cnt<6> &
div_cnt<7> & div_cnt<8> & div_cnt<9>;
div_cnt<22>.CLK = clk;
div_cnt<22>.AR = !rst;
MACROCELL | 0 | 4 | div_cnt<23>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 1 | 0 | 3
INPUTS | 25 | div_cnt<18> | div_cnt<19> | div_cnt<0> | div_cnt<10> | div_cnt<11> | div_cnt<12> | div_cnt<13> | div_cnt<14> | div_cnt<15> | div_cnt<16> | div_cnt<17> | div_cnt<1> | div_cnt<20> | div_cnt<21> | div_cnt<22> | div_cnt<2> | div_cnt<3> | div_cnt<4> | div_cnt<5> | div_cnt<6> | div_cnt<7> | div_cnt<8> | div_cnt<9> | clk | rst
INPUTMC | 23 | 0 | 9 | 0 | 8 | 1 | 10 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 1 | 17 | 0 | 7 | 0 | 6 | 0 | 5 | 1 | 16 | 1 | 15 | 1 | 14 | 1 | 13 | 1 | 12 | 0 | 2 | 0 | 1 | 0 | 0
INPUTP | 2 | 143 | 79
EQ | 8 |
div_cnt<23>.T = div_cnt<18> & div_cnt<19> & div_cnt<0> &
div_cnt<10> & div_cnt<11> & div_cnt<12> & div_cnt<13> &
div_cnt<14> & div_cnt<15> & div_cnt<16> & div_cnt<17> &
div_cnt<1> & div_cnt<20> & div_cnt<21> & div_cnt<22> &
div_cnt<2> & div_cnt<3> & div_cnt<4> & div_cnt<5> &
div_cnt<6> & div_cnt<7> & div_cnt<8> & div_cnt<9>;
div_cnt<23>.CLK = clk;
div_cnt<23>.AR = !rst;
MACROCELL | 1 | 16 | div_cnt<2>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 22 | 0 | 9 | 0 | 8 | 0 | 3 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 7 | 0 | 6 | 0 | 5 | 0 | 4 | 1 | 15 | 1 | 14 | 1 | 13 | 1 | 12 | 0 | 2 | 0 | 1 | 0 | 0
INPUTS | 4 | div_cnt<0> | div_cnt<1> | clk | rst
INPUTMC | 2 | 1 | 10 | 1 | 17
INPUTP | 2 | 143 | 79
EQ | 3 |
div_cnt<2>.T = div_cnt<0> & div_cnt<1>;
div_cnt<2>.CLK = clk;
div_cnt<2>.AR = !rst;
MACROCELL | 1 | 15 | div_cnt<3>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 21 | 0 | 9 | 0 | 8 | 0 | 3 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 7 | 0 | 6 | 0 | 5 | 0 | 4 | 1 | 14 | 1 | 13 | 1 | 12 | 0 | 2 | 0 | 1 | 0 | 0
INPUTS | 5 | div_cnt<0> | div_cnt<1> | div_cnt<2> | clk | rst
INPUTMC | 3 | 1 | 10 | 1 | 17 | 1 | 16
INPUTP | 2 | 143 | 79
EQ | 3 |
div_cnt<3>.T = div_cnt<0> & div_cnt<1> & div_cnt<2>;
div_cnt<3>.CLK = clk;
div_cnt<3>.AR = !rst;
MACROCELL | 1 | 14 | div_cnt<4>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 20 | 0 | 9 | 0 | 8 | 0 | 3 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 7 | 0 | 6 | 0 | 5 | 0 | 4 | 1 | 13 | 1 | 12 | 0 | 2 | 0 | 1 | 0 | 0
INPUTS | 6 | div_cnt<0> | div_cnt<1> | div_cnt<2> | div_cnt<3> | clk | rst
INPUTMC | 4 | 1 | 10 | 1 | 17 | 1 | 16 | 1 | 15
INPUTP | 2 | 143 | 79
EQ | 4 |
div_cnt<4>.T = div_cnt<0> & div_cnt<1> & div_cnt<2> &
div_cnt<3>;
div_cnt<4>.CLK = clk;
div_cnt<4>.AR = !rst;
MACROCELL | 1 | 13 | div_cnt<5>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 19 | 0 | 9 | 0 | 8 | 0 | 3 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 7 | 0 | 6 | 0 | 5 | 0 | 4 | 1 | 12 | 0 | 2 | 0 | 1 | 0 | 0
INPUTS | 7 | div_cnt<0> | div_cnt<1> | div_cnt<2> | div_cnt<3> | div_cnt<4> | clk | rst
INPUTMC | 5 | 1 | 10 | 1 | 17 | 1 | 16 | 1 | 15 | 1 | 14
INPUTP | 2 | 143 | 79
EQ | 4 |
div_cnt<5>.T = div_cnt<0> & div_cnt<1> & div_cnt<2> &
div_cnt<3> & div_cnt<4>;
div_cnt<5>.CLK = clk;
div_cnt<5>.AR = !rst;
MACROCELL | 1 | 12 | div_cnt<6>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 18 | 0 | 9 | 0 | 8 | 0 | 3 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 7 | 0 | 6 | 0 | 5 | 0 | 4 | 0 | 2 | 0 | 1 | 0 | 0
INPUTS | 8 | div_cnt<0> | div_cnt<1> | div_cnt<2> | div_cnt<3> | div_cnt<4> | div_cnt<5> | clk | rst
INPUTMC | 6 | 1 | 10 | 1 | 17 | 1 | 16 | 1 | 15 | 1 | 14 | 1 | 13
INPUTP | 2 | 143 | 79
EQ | 4 |
div_cnt<6>.T = div_cnt<0> & div_cnt<1> & div_cnt<2> &
div_cnt<3> & div_cnt<4> & div_cnt<5>;
div_cnt<6>.CLK = clk;
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