seg73.rpt

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

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********** Mapped Logic **********























FDCPE_cntfirst0: FDCPE port map (cntfirst(0),cntfirst_D(0),div_cnt(24),NOT rst,'0');
cntfirst_D(0) <= (NOT cntfirst(0) AND NOT last_over);

FDCPE_cntfirst1: FDCPE port map (cntfirst(1),en_xhdl(3).EXP,div_cnt(24),NOT rst,'0');

FTCPE_cntfirst2: FTCPE port map (cntfirst(2),cntfirst_T(2),div_cnt(24),NOT rst,'0');
cntfirst_T(2) <= ((cntfirst(2) AND last_over)
	OR (cntfirst(0) AND cntfirst(1) AND NOT last_over));

FTCPE_cntfirst3: FTCPE port map (cntfirst(3),cntfirst_T(3),div_cnt(24),NOT rst,'0');
cntfirst_T(3) <= ((cntfirst(3) AND last_over)
	OR (cntfirst(0) AND cntfirst(1) AND cntfirst(2) AND 
	NOT last_over)
	OR (cntfirst(0) AND NOT cntfirst(1) AND NOT cntfirst(2) AND 
	cntfirst(3)));

FTCPE_cntlast0: FTCPE port map (cntlast(0),'1',third_over,NOT rst,'0');

FTCPE_cntlast1: FTCPE port map (cntlast(1),cntlast_T(1),third_over,NOT rst,'0');
cntlast_T(1) <= ((NOT cntlast(0))
	OR (NOT cntlast(1) AND NOT cntlast(2) AND cntlast(3)));

FTCPE_cntlast2: FTCPE port map (cntlast(2),cntlast_T(2),third_over,NOT rst,'0');
cntlast_T(2) <= (cntlast(0) AND cntlast(1));

FTCPE_cntlast3: FTCPE port map (cntlast(3),cntlast_T(3),third_over,NOT rst,'0');
cntlast_T(3) <= ((cntlast(0) AND cntlast(1) AND cntlast(2))
	OR (cntlast(0) AND NOT cntlast(1) AND NOT cntlast(2) AND 
	cntlast(3)));

FTCPE_cntsecond0: FTCPE port map (cntsecond(0),'1',first_over,NOT rst,'0');

FTCPE_cntsecond1: FTCPE port map (cntsecond(1),cntsecond_T(1),first_over,NOT rst,'0');
cntsecond_T(1) <= ((NOT cntsecond(0))
	OR (NOT cntsecond(1) AND NOT cntsecond(2) AND cntsecond(3)));

FTCPE_cntsecond2: FTCPE port map (cntsecond(2),cntsecond_T(2),first_over,NOT rst,'0');
cntsecond_T(2) <= (cntsecond(0) AND cntsecond(1));

FTCPE_cntsecond3: FTCPE port map (cntsecond(3),cntsecond_T(3),first_over,NOT rst,'0');
cntsecond_T(3) <= ((cntsecond(0) AND cntsecond(1) AND cntsecond(2))
	OR (cntsecond(0) AND NOT cntsecond(1) AND NOT cntsecond(2) AND 
	cntsecond(3)));

FTCPE_cntthird0: FTCPE port map (cntthird(0),'1',second_over,NOT rst,'0');

FTCPE_cntthird1: FTCPE port map (cntthird(1),cntthird_T(1),second_over,NOT rst,'0');
cntthird_T(1) <= ((NOT cntthird(0))
	OR (NOT cntthird(1) AND NOT cntthird(2) AND cntthird(3)));

FTCPE_cntthird2: FTCPE port map (cntthird(2),cntthird_T(2),second_over,NOT rst,'0');
cntthird_T(2) <= (cntthird(0) AND cntthird(1));

FTCPE_cntthird3: FTCPE port map (cntthird(3),cntthird_T(3),second_over,NOT rst,'0');
cntthird_T(3) <= ((cntthird(0) AND cntthird(1) AND cntthird(2))
	OR (cntthird(0) AND NOT cntthird(1) AND NOT cntthird(2) AND 
	cntthird(3)));


dataout(0) <= '1';


dataout(1) <= ((en_xhdl(1).EXP)
	OR (EXP20_.EXP)
	OR (en(1) AND en(3) AND en(2) AND NOT en(0) AND NOT cntfirst(1) AND 
	NOT cntfirst(2) AND NOT cntfirst(3))
	OR (en(1) AND en(3) AND NOT en(2) AND en(0) AND NOT cntthird(1) AND 
	NOT cntthird(2) AND NOT cntthird(3))
	OR (en(1) AND NOT en(3) AND en(2) AND en(0) AND NOT cntlast(1) AND 
	NOT cntlast(2) AND NOT cntlast(3))
	OR (NOT en(1) AND en(3) AND en(2) AND en(0) AND NOT cntsecond(1) AND 
	NOT cntsecond(2) AND NOT cntsecond(3))
	OR (NOT en(1) AND en(3) AND en(2) AND en(0) AND NOT cntsecond(0) AND 
	NOT cntsecond(1) AND cntsecond(2) AND cntsecond(3)));


dataout(2)_BUFR <= ((EXP13_.EXP)
	OR (EXP14_.EXP)
	OR (en(1) AND en(3) AND en(2) AND NOT en(0) AND cntfirst(0) AND 
	cntfirst(1) AND NOT cntfirst(3))
	OR (en(1) AND en(3) AND NOT en(2) AND en(0) AND cntthird(0) AND 
	cntthird(1) AND NOT cntthird(3))
	OR (en(1) AND NOT en(3) AND en(2) AND en(0) AND cntlast(0) AND 
	cntlast(1) AND NOT cntlast(3))
	OR (NOT en(1) AND en(3) AND en(2) AND en(0) AND cntsecond(0) AND 
	cntsecond(1) AND NOT cntsecond(3))
	OR (NOT en(1) AND en(3) AND en(2) AND en(0) AND cntsecond(0) AND 
	NOT cntsecond(2) AND NOT cntsecond(3)));


dataout(2) <= dataout(2)_BUFR;


dataout(3) <= ((_12_.EXP)
	OR (dataout_0_OBUF.EXP)
	OR (en(1) AND en(3) AND en(2) AND NOT en(0) AND cntfirst(0) AND 
	NOT cntfirst(3))
	OR (en(1) AND en(3) AND NOT en(2) AND en(0) AND cntthird(0) AND 
	NOT cntthird(3))
	OR (en(1) AND NOT en(3) AND en(2) AND en(0) AND cntlast(0) AND 
	NOT cntlast(3))
	OR (NOT en(1) AND en(3) AND en(2) AND en(0) AND cntsecond(0) AND 
	NOT cntsecond(3))
	OR (NOT en(1) AND en(3) AND en(2) AND en(0) AND NOT cntsecond(1) AND 
	cntsecond(2) AND NOT cntsecond(3)));


dataout(4) <= dataout(4)_BUFR;


dataout(4)_BUFR <= ((EXP17_.EXP)
	OR (EXP18_.EXP)
	OR (NOT en(3) AND NOT cntlast(0) AND cntlast(1) AND NOT cntlast(2) AND 
	cntlast(3))
	OR (NOT en(2) AND NOT cntthird(0) AND cntthird(1) AND NOT cntthird(2) AND 
	cntthird(3))
	OR (NOT en(2) AND NOT cntthird(0) AND NOT cntthird(1) AND cntthird(2) AND 
	NOT cntthird(3))
	OR (NOT en(0) AND NOT cntfirst(0) AND cntfirst(1) AND NOT cntfirst(2) AND 
	cntfirst(3))
	OR (NOT en(0) AND NOT cntfirst(0) AND NOT cntfirst(1) AND cntfirst(2) AND 
	NOT cntfirst(3)));


dataout(5) <= ((EXP21_.EXP)
	OR (EXP22_.EXP)
	OR (en(1) AND en(3) AND NOT en(2) AND en(0) AND NOT cntthird(0) AND 
	cntthird(2) AND cntthird(3))
	OR (en(1) AND NOT en(3) AND en(2) AND en(0) AND NOT cntlast(0) AND 
	cntlast(2) AND cntlast(3))
	OR (en(1) AND NOT en(3) AND en(2) AND en(0) AND cntlast(1) AND 
	cntlast(2) AND cntlast(3))
	OR (NOT en(1) AND en(3) AND en(2) AND en(0) AND NOT cntsecond(0) AND 
	cntsecond(2) AND cntsecond(3))
	OR (NOT en(1) AND en(3) AND en(2) AND en(0) AND cntsecond(1) AND 
	cntsecond(2) AND cntsecond(3)));


dataout(6) <= ((cntlast(0).EXP)
	OR (EXP23_.EXP)
	OR (en(1) AND en(3) AND en(2) AND NOT en(0) AND cntfirst(0) AND 
	cntfirst(1) AND cntfirst(3))
	OR (en(1) AND en(3) AND NOT en(2) AND en(0) AND cntthird(0) AND 
	cntthird(1) AND cntthird(3))
	OR (en(1) AND NOT en(3) AND en(2) AND en(0) AND cntlast(0) AND 
	cntlast(1) AND cntlast(3))
	OR (NOT en(1) AND en(3) AND en(2) AND en(0) AND cntsecond(0) AND 
	cntsecond(1) AND cntsecond(3))
	OR (NOT en(1) AND en(3) AND en(2) AND en(0) AND NOT cntsecond(0) AND 
	cntsecond(1) AND cntsecond(2)));


dataout(7)_BUFR <= ((EXP15_.EXP)
	OR (NOT en(1) AND en(3) AND en(2) AND en(0) AND cntsecond(0) AND 
	cntsecond(1) AND NOT cntsecond(2) AND cntsecond(3))
	OR (NOT en(1) AND en(3) AND en(2) AND en(0) AND cntsecond(0) AND 
	NOT cntsecond(1) AND cntsecond(2) AND cntsecond(3))
	OR (NOT en(1) AND en(3) AND en(2) AND en(0) AND cntsecond(0) AND 
	NOT cntsecond(1) AND NOT cntsecond(2) AND NOT cntsecond(3))
	OR (NOT en(1) AND en(3) AND en(2) AND en(0) AND NOT cntsecond(0) AND 
	NOT cntsecond(1) AND cntsecond(2) AND NOT cntsecond(3)));


dataout(7) <= dataout(7)_BUFR;

FTCPE_div_cnt0: FTCPE port map (div_cnt(0),'1',clk,NOT rst,'0');

FTCPE_div_cnt1: FTCPE port map (div_cnt(1),div_cnt(0),clk,NOT rst,'0');

FTCPE_div_cnt2: FTCPE port map (div_cnt(2),div_cnt_T(2),clk,NOT rst,'0');
div_cnt_T(2) <= (div_cnt(0) AND div_cnt(1));

FTCPE_div_cnt3: FTCPE port map (div_cnt(3),div_cnt_T(3),clk,NOT rst,'0');
div_cnt_T(3) <= (div_cnt(0) AND div_cnt(1) AND div_cnt(2));

FTCPE_div_cnt4: FTCPE port map (div_cnt(4),div_cnt_T(4),clk,NOT rst,'0');
div_cnt_T(4) <= (div_cnt(0) AND div_cnt(1) AND div_cnt(2) AND 
	div_cnt(3));

FTCPE_div_cnt5: FTCPE port map (div_cnt(5),div_cnt_T(5),clk,NOT rst,'0');
div_cnt_T(5) <= (div_cnt(0) AND div_cnt(1) AND div_cnt(2) AND 
	div_cnt(3) AND div_cnt(4));

FTCPE_div_cnt6: FTCPE port map (div_cnt(6),div_cnt_T(6),clk,NOT rst,'0');
div_cnt_T(6) <= (div_cnt(0) AND div_cnt(1) AND div_cnt(2) AND 
	div_cnt(3) AND div_cnt(4) AND div_cnt(5));

FTCPE_div_cnt7: FTCPE port map (div_cnt(7),div_cnt_T(7),clk,NOT rst,'0');
div_cnt_T(7) <= (div_cnt(0) AND div_cnt(1) AND div_cnt(2) AND 
	div_cnt(3) AND div_cnt(4) AND div_cnt(5) AND div_cnt(6));

FTCPE_div_cnt8: FTCPE port map (div_cnt(8),div_cnt_T(8),clk,NOT rst,'0');
div_cnt_T(8) <= (div_cnt(0) AND div_cnt(1) AND div_cnt(2) AND 
	div_cnt(3) AND div_cnt(4) AND div_cnt(5) AND div_cnt(6) AND 
	div_cnt(7));

FTCPE_div_cnt9: FTCPE port map (div_cnt(9),div_cnt_T(9),clk,NOT rst,'0');
div_cnt_T(9) <= (div_cnt(0) AND div_cnt(1) AND div_cnt(2) AND 
	div_cnt(3) AND div_cnt(4) AND div_cnt(5) AND div_cnt(6) AND 
	div_cnt(7) AND div_cnt(8));

FTCPE_div_cnt10: FTCPE port map (div_cnt(10),div_cnt_T(10),clk,NOT rst,'0');
div_cnt_T(10) <= (div_cnt(0) AND div_cnt(1) AND div_cnt(2) AND 
	div_cnt(3) AND div_cnt(4) AND div_cnt(5) AND div_cnt(6) AND 
	div_cnt(7) AND div_cnt(8) AND div_cnt(9));

FTCPE_div_cnt11: FTCPE port map (div_cnt(11),div_cnt_T(11),clk,NOT rst,'0');
div_cnt_T(11) <= (div_cnt(0) AND div_cnt(10) AND div_cnt(1) AND 
	div_cnt(2) AND div_cnt(3) AND div_cnt(4) AND div_cnt(5) AND 
	div_cnt(6) AND div_cnt(7) AND div_cnt(8) AND div_cnt(9));

FTCPE_div_cnt12: FTCPE port map (div_cnt(12),div_cnt_T(12),clk,NOT rst,'0');
div_cnt_T(12) <= (div_cnt(0) AND div_cnt(10) AND div_cnt(11) AND 
	div_cnt(1) AND div_cnt(2) AND div_cnt(3) AND div_cnt(4) AND