seg73.syr

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

  Destination:       cntfirst_3 (FF)
  Source Clock:      div_cnt_24:Q rising
  Destination Clock: div_cnt_24:Q rising

  Data Path: cntfirst_1 to cntfirst_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q            4   1.292   1.600  cntfirst_1 (cntfirst_1)
     LUT2_D:I1->LO         1   0.653   0.100  _n00151_SW0 (N72)
     LUT4_D:I2->O          1   0.653   1.150  _n00151 (_n0015)
     LUT1_L:I0->LO         1   0.653   0.000  _n0015_rt (_n0015_rt)
     MUXCY:S->O            1   0.784   0.000  cntfirst_inst_cy_0 (cntfirst_inst_cy_0)
     MUXCY:CI->O           1   0.050   0.000  cntfirst_inst_cy_1 (cntfirst_inst_cy_1)
     MUXCY:CI->O           1   0.050   0.000  cntfirst_inst_cy_2 (cntfirst_inst_cy_2)
     MUXCY:CI->O           0   0.050   0.000  cntfirst_inst_cy_3 (cntfirst_inst_cy_3)
     XORCY:CI->O           1   0.500   0.000  cntfirst_inst_sum_3 (cntfirst_inst_sum_3)
     FDCPE:D                   0.753          cntfirst_3
    ----------------------------------------
    Total                      8.288ns (5.438ns logic, 2.850ns route)
                                       (65.6% logic, 34.4% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'first_over:Q'
  Clock period: 5.872ns (frequency: 170.300MHz)
  Total number of paths / destination ports: 45 / 5
-------------------------------------------------------------------------
Delay:               5.872ns (Levels of Logic = 6)
  Source:            cntsecond_1 (FF)
  Destination:       cntsecond_3 (FF)
  Source Clock:      first_over:Q rising
  Destination Clock: first_over:Q rising

  Data Path: cntsecond_1 to cntsecond_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q            5   1.292   1.740  cntsecond_1 (cntsecond_1)
     LUT4_L:I1->LO         2   0.653   0.000  _n00141 (_n0014)
     MUXCY:S->O            1   0.784   0.000  cntsecond_inst_cy_0 (cntsecond_inst_cy_0)
     MUXCY:CI->O           1   0.050   0.000  cntsecond_inst_cy_1 (cntsecond_inst_cy_1)
     MUXCY:CI->O           1   0.050   0.000  cntsecond_inst_cy_2 (cntsecond_inst_cy_2)
     MUXCY:CI->O           0   0.050   0.000  cntsecond_inst_cy_3 (cntsecond_inst_cy_3)
     XORCY:CI->O           1   0.500   0.000  cntsecond_inst_sum_3 (cntsecond_inst_sum_3)
     FDCPE:D                   0.753          cntsecond_3
    ----------------------------------------
    Total                      5.872ns (4.132ns logic, 1.740ns route)
                                       (70.4% logic, 29.6% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 6.282ns (frequency: 159.185MHz)
  Total number of paths / destination ports: 333 / 29
-------------------------------------------------------------------------
Delay:               6.282ns (Levels of Logic = 26)
  Source:            div_cnt_0 (FF)
  Destination:       div_cnt_24 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: div_cnt_0 to div_cnt_24
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              1   1.292   1.150  div_cnt_0 (div_cnt_0)
     INV:I->O              2   0.653   0.000  seg73_div_cnt__n0000<0>lut_INV_0 (N3)
     MUXCY:S->O            1   0.784   0.000  seg73_div_cnt__n0000<0>cy (seg73_div_cnt__n0000<0>_cyo)
     MUXCY:CI->O           1   0.050   0.000  seg73_div_cnt__n0000<1>cy (seg73_div_cnt__n0000<1>_cyo)
     MUXCY:CI->O           1   0.050   0.000  seg73_div_cnt__n0000<2>cy (seg73_div_cnt__n0000<2>_cyo)
     MUXCY:CI->O           1   0.050   0.000  seg73_div_cnt__n0000<3>cy (seg73_div_cnt__n0000<3>_cyo)
     MUXCY:CI->O           1   0.050   0.000  seg73_div_cnt__n0000<4>cy (seg73_div_cnt__n0000<4>_cyo)
     MUXCY:CI->O           1   0.050   0.000  seg73_div_cnt__n0000<5>cy (seg73_div_cnt__n0000<5>_cyo)
     MUXCY:CI->O           1   0.050   0.000  seg73_div_cnt__n0000<6>cy (seg73_div_cnt__n0000<6>_cyo)
     MUXCY:CI->O           1   0.050   0.000  seg73_div_cnt__n0000<7>cy (seg73_div_cnt__n0000<7>_cyo)
     MUXCY:CI->O           1   0.050   0.000  seg73_div_cnt__n0000<8>cy (seg73_div_cnt__n0000<8>_cyo)
     MUXCY:CI->O           1   0.050   0.000  seg73_div_cnt__n0000<9>cy (seg73_div_cnt__n0000<9>_cyo)
     MUXCY:CI->O           1   0.050   0.000  seg73_div_cnt__n0000<10>cy (seg73_div_cnt__n0000<10>_cyo)
     MUXCY:CI->O           1   0.050   0.000  seg73_div_cnt__n0000<11>cy (seg73_div_cnt__n0000<11>_cyo)
     MUXCY:CI->O           1   0.050   0.000  seg73_div_cnt__n0000<12>cy (seg73_div_cnt__n0000<12>_cyo)
     MUXCY:CI->O           1   0.050   0.000  seg73_div_cnt__n0000<13>cy (seg73_div_cnt__n0000<13>_cyo)
     MUXCY:CI->O           1   0.050   0.000  seg73_div_cnt__n0000<14>cy (seg73_div_cnt__n0000<14>_cyo)
     MUXCY:CI->O           1   0.050   0.000  seg73_div_cnt__n0000<15>cy (seg73_div_cnt__n0000<15>_cyo)
     MUXCY:CI->O           1   0.050   0.000  seg73_div_cnt__n0000<16>cy (seg73_div_cnt__n0000<16>_cyo)
     MUXCY:CI->O           1   0.050   0.000  seg73_div_cnt__n0000<17>cy (seg73_div_cnt__n0000<17>_cyo)
     MUXCY:CI->O           1   0.050   0.000  seg73_div_cnt__n0000<18>cy (seg73_div_cnt__n0000<18>_cyo)
     MUXCY:CI->O           1   0.050   0.000  seg73_div_cnt__n0000<19>cy (seg73_div_cnt__n0000<19>_cyo)
     MUXCY:CI->O           1   0.050   0.000  seg73_div_cnt__n0000<20>cy (seg73_div_cnt__n0000<20>_cyo)
     MUXCY:CI->O           1   0.050   0.000  seg73_div_cnt__n0000<21>cy (seg73_div_cnt__n0000<21>_cyo)
     MUXCY:CI->O           1   0.050   0.000  seg73_div_cnt__n0000<22>cy (seg73_div_cnt__n0000<22>_cyo)
     MUXCY:CI->O           0   0.050   0.000  seg73_div_cnt__n0000<23>cy (seg73_div_cnt__n0000<23>_cyo)
     XORCY:CI->O           1   0.500   0.000  seg73_div_cnt__n0000<24>_xor (div_cnt__n0000<24>)
     FDC:D                     0.753          div_cnt_24
    ----------------------------------------
    Total                      6.282ns (5.132ns logic, 1.150ns route)
                                       (81.7% logic, 18.3% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'second_over:Q'
  Clock period: 5.872ns (frequency: 170.300MHz)
  Total number of paths / destination ports: 45 / 5
-------------------------------------------------------------------------
Delay:               5.872ns (Levels of Logic = 6)
  Source:            cntthird_1 (FF)
  Destination:       cntthird_3 (FF)
  Source Clock:      second_over:Q rising
  Destination Clock: second_over:Q rising

  Data Path: cntthird_1 to cntthird_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q            5   1.292   1.740  cntthird_1 (cntthird_1)
     LUT4_L:I1->LO         2   0.653   0.000  _n00091 (_n0009)
     MUXCY:S->O            1   0.784   0.000  cntthird_inst_cy_0 (cntthird_inst_cy_0)
     MUXCY:CI->O           1   0.050   0.000  cntthird_inst_cy_1 (cntthird_inst_cy_1)
     MUXCY:CI->O           1   0.050   0.000  cntthird_inst_cy_2 (cntthird_inst_cy_2)
     MUXCY:CI->O           0   0.050   0.000  cntthird_inst_cy_3 (cntthird_inst_cy_3)
     XORCY:CI->O           1   0.500   0.000  cntthird_inst_sum_3 (cntthird_inst_sum_3)
     FDCPE:D                   0.753          cntthird_3
    ----------------------------------------
    Total                      5.872ns (4.132ns logic, 1.740ns route)
                                       (70.4% logic, 29.6% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'third_over:Q'
  Clock period: 5.872ns (frequency: 170.300MHz)
  Total number of paths / destination ports: 45 / 5
-------------------------------------------------------------------------
Delay:               5.872ns (Levels of Logic = 6)
  Source:            cntlast_1 (FF)
  Destination:       cntlast_3 (FF)
  Source Clock:      third_over:Q rising
  Destination Clock: third_over:Q rising

  Data Path: cntlast_1 to cntlast_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q            5   1.292   1.740  cntlast_1 (cntlast_1)
     LUT4_L:I1->LO         2   0.653   0.000  _n00131 (_n0013)
     MUXCY:S->O            1   0.784   0.000  cntlast_inst_cy_0 (cntlast_inst_cy_0)
     MUXCY:CI->O           1   0.050   0.000  cntlast_inst_cy_1 (cntlast_inst_cy_1)
     MUXCY:CI->O           1   0.050   0.000  cntlast_inst_cy_2 (cntlast_inst_cy_2)
     MUXCY:CI->O           0   0.050   0.000  cntlast_inst_cy_3 (cntlast_inst_cy_3)
     XORCY:CI->O           1   0.500   0.000  cntlast_inst_sum_3 (cntlast_inst_sum_3)
     FDCPE:D                   0.753          cntlast_3
    ----------------------------------------
    Total                      5.872ns (4.132ns logic, 1.740ns route)
                                       (70.4% logic, 29.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 508 / 11
-------------------------------------------------------------------------
Offset:              18.964ns (Levels of Logic = 6)
  Source:            en_xhdl_3 (FF)
  Destination:       dataout<7> (PAD)
  Source Clock:      clk rising

  Data Path: en_xhdl_3 to dataout<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDP:C->Q              6   1.292   1.850  en_xhdl_3 (en_xhdl_3)
     LUT4:I3->O            4   0.653   1.600  _n00211 (_n0021)
     LUT4:I2->O            1   0.653   1.150  data4<3>8 (CHOICE125)
     LUT3:I0->O            1   0.653   1.150  data4<3>10 (CHOICE126)
     LUT4:I1->O            7   0.653   1.950  data4<3>16 (data4<3>)
     LUT4:I3->O            1   0.653   1.150  Mrom_dataout_xhdl1_inst_lut4_71 (dataout_7_OBUF)
     OBUF:I->O                 5.557          dataout_7_OBUF (dataout<7>)
    ----------------------------------------
    Total                     18.964ns (10.114ns logic, 8.850ns route)
                                       (53.3% logic, 46.7% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'second_over:Q'
  Total number of paths / destination ports: 28 / 7
-------------------------------------------------------------------------
Offset:              16.601ns (Levels of Logic = 5)
  Source:            cntthird_1 (FF)
  Destination:       dataout<7> (PAD)
  Source Clock:      second_over:Q rising

  Data Path: cntthird_1 to dataout<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q            5   1.292   1.740  cntthird_1 (cntthird_1)
     LUT4:I1->O            1   0.653   1.150  data4<1>8 (CHOICE133)
     LUT3:I0->O            1   0.653   1.150  data4<1>10 (CHOICE134)
     LUT4:I1->O            7   0.653   1.950  data4<1>16 (data4<1>)
     LUT4:I1->O            1   0.653   1.150  Mrom_dataout_xhdl1_inst_lut4_71 (dataout_7_OBUF)
     OBUF:I->O                 5.557          dataout_7_OBUF (dataout<7>)
    ----------------------------------------
    Total                     16.601ns (9.461ns logic, 7.140ns route)
                                       (57.0% logic, 43.0% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'third_over:Q'
  Total number of paths / destination ports: 28 / 7
-------------------------------------------------------------------------
Offset:              16.601ns (Levels of Logic = 5)
  Source:            cntlast_1 (FF)
  Destination:       dataout<7> (PAD)
  Source Clock:      third_over:Q rising

  Data Path: cntlast_1 to dataout<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q            5   1.292   1.740  cntlast_1 (cntlast_1)
     LUT4:I3->O            1   0.653   1.150  data4<1>8 (CHOICE133)
     LUT3:I0->O            1   0.653   1.150  data4<1>10 (CHOICE134)
     LUT4:I1->O            7   0.653   1.950  data4<1>16 (data4<1>)
     LUT4:I1->O            1   0.653   1.150  Mrom_dataout_xhdl1_inst_lut4_71 (dataout_7_OBUF)
     OBUF:I->O                 5.557          dataout_7_OBUF (dataout<7>)
    ----------------------------------------
    Total                     16.601ns (9.461ns logic, 7.140ns route)
                                       (57.0% logic, 43.0% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'div_cnt_24:Q'
  Total number of paths / destination ports: 28 / 7
-------------------------------------------------------------------------
Offset:              14.798ns (Levels of Logic = 4)
  Source:            cntfirst_2 (FF)
  Destination:       dataout<7> (PAD)
  Source Clock:      div_cnt_24:Q rising

  Data Path: cntfirst_2 to dataout<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q            5   1.292   1.740  cntfirst_2 (cntfirst_2)
     LUT4:I1->O            1   0.653   1.150  data4<2>9 (CHOICE111)
     LUT2:I1->O            7   0.653   1.950  data4<2>10 (data4<2>)
     LUT4:I2->O            1   0.653   1.150  Mrom_dataout_xhdl1_inst_lut4_71 (dataout_7_OBUF)
     OBUF:I->O                 5.557          dataout_7_OBUF (dataout<7>)
    ----------------------------------------
    Total                     14.798ns (8.808ns logic, 5.990ns route)
                                       (59.5% logic, 40.5% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'first_over:Q'
  Total number of paths / destination ports: 28 / 7
-------------------------------------------------------------------------
Offset:              14.798ns (Levels of Logic = 4)
  Source:            cntsecond_1 (FF)
  Destination:       dataout<7> (PAD)
  Source Clock:      first_over:Q rising

  Data Path: cntsecond_1 to dataout<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q            5   1.292   1.740  cntsecond_1 (cntsecond_1)
     LUT3:I2->O            1   0.653   1.150  data4<1>10 (CHOICE134)
     LUT4:I1->O            7   0.653   1.950  data4<1>16 (data4<1>)
     LUT4:I1->O            1   0.653   1.150  Mrom_dataout_xhdl1_inst_lut4_71 (dataout_7_OBUF)
     OBUF:I->O                 5.557          dataout_7_OBUF (dataout<7>)
    ----------------------------------------
    Total                     14.798ns (8.808ns logic, 5.990ns route)
                                       (59.5% logic, 40.5% route)

=========================================================================
CPU : 5.74 / 6.27 s | Elapsed : 5.00 / 6.00 s
 
--> 

Total memory usage is 75780 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    2 (   0 filtered)
Number of infos    :    2 (   0 filtered)