keyscan.syr

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

Release 7.1.04i - xst H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: keyscan.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "keyscan.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "keyscan"
Output Format                      : NGC
Target Device                      : xc2s50-6-TQ144

---- Source Options
Top Module Name                    : keyscan
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : keyscan.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
tristate2logic                     : Yes
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3215 - Unit work/KEYSCAN is now defined in a different file: was E:/temp/95144/vhdl/KeyScan/KEYSCAN.vhd, now is E:/temp/SPARTAN2/vhdl/Interface/KeyScan/KEYSCAN.vhd
WARNING:HDLParsers:3215 - Unit work/KEYSCAN/ARCH is now defined in a different file: was E:/temp/95144/vhdl/KeyScan/KEYSCAN.vhd, now is E:/temp/SPARTAN2/vhdl/Interface/KeyScan/KEYSCAN.vhd
Compiling vhdl file "E:/temp/SPARTAN2/vhdl/Interface/KeyScan/KEYSCAN.vhd" in Library work.
Architecture arch of Entity keyscan is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <keyscan> (Architecture <arch>).
Entity <keyscan> analyzed. Unit <keyscan> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <keyscan>.
    Related source file is "E:/temp/SPARTAN2/vhdl/Interface/KeyScan/KEYSCAN.vhd".
    Using one-hot encoding for signal <key_code>.
    Found 25-bit up counter for signal <div_cnt>.
    Found 16-bit register for signal <key_code>.
    Found 1-of-4 decoder for signal <scan_key>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 Decoder(s).
Unit <keyscan> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 1
 25-bit up counter                 : 1
# Registers                        : 1
 16-bit register                   : 1
# Decoders                         : 1
 1-of-4 decoder                    : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1291 - FF/Latch <div_cnt_23> is unconnected in block <keyscan>.
WARNING:Xst:1291 - FF/Latch <div_cnt_24> is unconnected in block <keyscan>.
WARNING:Xst:1291 - FF/Latch <div_cnt_21> is unconnected in block <keyscan>.
WARNING:Xst:1291 - FF/Latch <div_cnt_22> is unconnected in block <keyscan>.

Optimizing unit <keyscan> ...
Loading device for application Rf_Device from file 'v50.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block keyscan, actual ratio is 5.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : keyscan.ngr
Top Level Output File Name         : keyscan
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 26

Macro Statistics :
# Registers                        : 17
#      1-bit register              : 16
#      25-bit register             : 1
# Decoders                         : 1
#      1-of-4 decoder              : 1
# Adders/Subtractors               : 1
#      25-bit adder                : 1

Cell Usage :
# BELS                             : 118
#      GND                         : 1
#      INV                         : 2
#      LUT1                        : 14
#      LUT1_L                      : 6
#      LUT2                        : 7
#      LUT2_D                      : 5
#      LUT2_L                      : 3
#      LUT3                        : 3
#      LUT4                        : 18
#      LUT4_D                      : 2
#      LUT4_L                      : 16
#      MUXCY                       : 20
#      VCC                         : 1
#      XORCY                       : 20
# FlipFlops/Latches                : 37
#      FDC                         : 36
#      FDP                         : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 25
#      IBUF                        : 5
#      OBUF                        : 20
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-6 

 Number of Slices:                      40  out of    768     5%  
 Number of Slice Flip Flops:            37  out of   1536     2%  
 Number of 4 input LUTs:                74  out of   1536     4%  
 Number of bonded IOBs:                 26  out of     96    27%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 37    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 8.139ns (Maximum Frequency: 122.865MHz)
   Minimum input arrival time before clock: 7.597ns
   Maximum output required time after clock: 12.260ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 8.139ns (frequency: 122.865MHz)
  Total number of paths / destination ports: 297 / 37
-------------------------------------------------------------------------
Delay:               8.139ns (Levels of Logic = 3)
  Source:            div_cnt_20 (FF)
  Destination:       key_code_0 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: div_cnt_20 to key_code_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             12   1.085   2.160  div_cnt_20 (div_cnt_20)
     LUT2_D:I0->O          3   0.549   1.332  Mdecod_scan_key_inst_inv_21 (row_2_OBUF)
     LUT4_D:I3->O          2   0.549   1.206  Ker16 (N16)
     LUT4_L:I2->LO         1   0.549   0.000  _n0000<4>1 (_n0000<4>)
     FDC:D                     0.709          key_code_4
    ----------------------------------------
    Total                      8.139ns (3.441ns logic, 4.698ns route)
                                       (42.3% logic, 57.7% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 128 / 16
-------------------------------------------------------------------------
Offset:              7.597ns (Levels of Logic = 4)
  Source:            column<0> (PAD)
  Destination:       key_code_15 (FF)
  Destination Clock: clk rising

  Data Path: column<0> to key_code_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             8   0.776   1.845  column_0_IBUF (column_0_IBUF)
     LUT4:I0->O           16   0.549   2.520  _n00171 (_n0017)
     LUT2_L:I1->LO         1   0.549   0.100  _n0000<15>90_SW0 (N151)
     LUT4_L:I3->LO         1   0.549   0.000  _n0000<15>90 (_n0000<15>)
     FDC:D                     0.709          key_code_15
    ----------------------------------------
    Total                      7.597ns (3.132ns logic, 4.465ns route)
                                       (41.2% logic, 58.8% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 59 / 12
-------------------------------------------------------------------------
Offset:              12.260ns (Levels of Logic = 4)
  Source:            key_code_1 (FF)
  Destination:       dataout<0> (PAD)
  Source Clock:      clk rising

  Data Path: key_code_1 to dataout<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              7   1.085   1.755  key_code_1 (key_code_1)
     LUT4:I3->O            1   0.549   1.035  dataout_tmp<0>26 (CHOICE1034)
     LUT4:I1->O            1   0.549   1.035  dataout_tmp<0>35_SW0 (N153)
     LUT4:I3->O            1   0.549   1.035  dataout_tmp<0>35 (dataout_0_OBUF)
     OBUF:I->O                 4.668          dataout_0_OBUF (dataout<0>)
    ----------------------------------------
    Total                     12.260ns (7.400ns logic, 4.860ns route)
                                       (60.4% logic, 39.6% route)

=========================================================================
CPU : 6.95 / 7.50 s | Elapsed : 7.00 / 7.00 s
 
--> 

Total memory usage is 78852 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    6 (   0 filtered)
Number of infos    :    0 (   0 filtered)