keyscan.rpt
来自「Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档」· RPT 代码 · 共 772 行 · 第 1/3 页
RPT
772 行
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
dataout<1> .................XXXX................... 4
en<2> ........................................ 0
en<6> ........................................ 0
div_cnt<0> X....................X.................. 2
en<0> ........................................ 0
div_cnt<1> XX...................X.................. 3
en<1> ........................................ 0
en<7> ........................................ 0
div_cnt<16> XXXXXXXXXXXXXXXXX....X.................. 18
div_cnt<15> XXXXXXX.XXXXXXXXX....X.................. 17
div_cnt<14> XXXXXX..XXXXXXXXX....X.................. 16
div_cnt<13> XXXXX...XXXXXXXXX....X.................. 15
div_cnt<12> XXXX....XXXXXXXXX....X.................. 14
div_cnt<11> XXX.....XXXXXXXXX....X.................. 13
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB5 ***********************************
Number of function block inputs used/remaining: 0/54
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB5_1 (b)
(unused) 0 0 0 5 FB5_2 52 I/O
(unused) 0 0 0 5 FB5_3 59 I/O
(unused) 0 0 0 5 FB5_4 (b)
(unused) 0 0 0 5 FB5_5 53 I/O
(unused) 0 0 0 5 FB5_6 54 I/O
(unused) 0 0 0 5 FB5_7 66 I/O
(unused) 0 0 0 5 FB5_8 56 I/O
(unused) 0 0 0 5 FB5_9 57 I/O
(unused) 0 0 0 5 FB5_10 68 I/O
(unused) 0 0 0 5 FB5_11 58 I/O
(unused) 0 0 0 5 FB5_12 60 I/O
(unused) 0 0 0 5 FB5_13 70 I/O
(unused) 0 0 0 5 FB5_14 61 I/O
(unused) 0 0 0 5 FB5_15 64 I/O
(unused) 0 0 0 5 FB5_16 (b)
(unused) 0 0 0 5 FB5_17 69 I/O
(unused) 0 0 0 5 FB5_18 (b)
*********************************** FB6 ***********************************
Number of function block inputs used/remaining: 4/50
Number of signals used by logic mapping into function block: 4
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB6_1 (b)
dataout<7> 4 0 0 1 FB6_2 106 I/O O
(unused) 0 0 0 5 FB6_3 (b)
dataout<5> 3 0 0 2 FB6_4 111 I/O O
(unused) 0 0 0 5 FB6_5 110 I/O
(unused) 0 0 0 5 FB6_6 112 I/O
(unused) 0 0 0 5 FB6_7 (b)
dataout<4> 4 0 0 1 FB6_8 113 I/O O
dataout<2> 4 0 0 1 FB6_9 116 I/O O
dataout<3> 3 0 0 2 FB6_10 115 I/O O
dataout<0> 0 0 0 5 FB6_11 119 I/O O
en<3> 0 0 0 5 FB6_12 120 I/O O
(unused) 0 0 0 5 FB6_13 (b)
(unused) 0 0 0 5 FB6_14 121 I/O
en<4> 0 0 0 5 FB6_15 124 I/O O
(unused) 0 0 0 5 FB6_16 117 I/O
en<5> 0 0 0 5 FB6_17 125 I/O O
(unused) 0 0 0 5 FB6_18 (b)
Signals Used by Logic in Function Block
1: key_code<0> 3: key_code<2> 4: key_code<3>
2: key_code<1>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
dataout<7> XXXX.................................... 4
dataout<5> XXXX.................................... 4
dataout<4> XXXX.................................... 4
dataout<2> XXXX.................................... 4
dataout<3> XXXX.................................... 4
dataout<0> ........................................ 0
en<3> ........................................ 0
en<4> ........................................ 0
en<5> ........................................ 0
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB7 ***********************************
Number of function block inputs used/remaining: 0/54
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB7_1 (b)
(unused) 0 0 0 5 FB7_2 71 I/O I
(unused) 0 0 0 5 FB7_3 75 I/O
(unused) 0 0 0 5 FB7_4 (b)
(unused) 0 0 0 5 FB7_5 74 I/O
(unused) 0 0 0 5 FB7_6 76 I/O
(unused) 0 0 0 5 FB7_7 77 I/O
(unused) 0 0 0 5 FB7_8 78 I/O
(unused) 0 0 0 5 FB7_9 80 I/O
(unused) 0 0 0 5 FB7_10 79 I/O
(unused) 0 0 0 5 FB7_11 82 I/O
(unused) 0 0 0 5 FB7_12 85 I/O
(unused) 0 0 0 5 FB7_13 81 I/O
(unused) 0 0 0 5 FB7_14 86 I/O
(unused) 0 0 0 5 FB7_15 87 I/O
(unused) 0 0 0 5 FB7_16 83 I/O
(unused) 0 0 0 5 FB7_17 88 I/O
(unused) 0 0 0 5 FB7_18 (b)
*********************************** FB8 ***********************************
Number of function block inputs used/remaining: 22/32
Number of signals used by logic mapping into function block: 22
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
key_code<2> 10 5<- 0 0 FB8_1 (b) (b)
row<3> 1 1<- /\5 0 FB8_2 91 I/O O
div_cnt<7> 3 0 /\1 1 FB8_3 95 I/O (b)
div_cnt<8> 3 0 0 2 FB8_4 97 I/O I
row<2> 1 0 0 4 FB8_5 92 I/O O
row<1> 1 0 0 4 FB8_6 93 I/O O
div_cnt<6> 3 0 0 2 FB8_7 (b) (b)
row<0> 1 0 0 4 FB8_8 94 I/O O
div_cnt<3> 3 0 0 2 FB8_9 96 I/O I
div_cnt<4> 3 0 0 2 FB8_10 101 I/O (b)
div_cnt<2> 3 0 0 2 FB8_11 98 I/O I
div_cnt<10> 3 0 \/2 0 FB8_12 100 I/O I
key_code<1> 6 2<- \/1 0 FB8_13 103 I/O (b)
key_code<0> 6 1<- 0 0 FB8_14 102 I/O (b)
div_cnt<5> 3 0 \/2 0 FB8_15 104 I/O (b)
dataout<6> 4 2<- \/3 0 FB8_16 107 I/O O
key_code<3> 10 5<- 0 0 FB8_17 105 I/O (b)
div_cnt<9> 3 0 /\2 0 FB8_18 (b) (b)
Signals Used by Logic in Function Block
1: clk 9: div_cnt<20> 16: div_cnt<8>
2: column<0> 10: div_cnt<2> 17: div_cnt<9>
3: column<1> 11: div_cnt<3> 18: key_code<0>
4: column<2> 12: div_cnt<4> 19: key_code<1>
5: column<3> 13: div_cnt<5> 20: key_code<2>
6: div_cnt<0> 14: div_cnt<6> 21: key_code<3>
7: div_cnt<19> 15: div_cnt<7> 22: rst
8: div_cnt<1>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
key_code<2> XXXXX.X............X.X.................. 8
row<3> ......X.X............................... 2
div_cnt<7> X....X.X.XXXXX.......X.................. 9
div_cnt<8> X....X.X.XXXXXX......X.................. 10
row<2> ......X.X............................... 2
row<1> ......X.X............................... 2
div_cnt<6> X....X.X.XXXX........X.................. 8
row<0> ......X.X............................... 2
div_cnt<3> X....X.X.X...........X.................. 5
div_cnt<4> X....X.X.XX..........X.................. 6
div_cnt<2> X....X.X.............X.................. 4
div_cnt<10> X....X.X.XXXXXXXX....X.................. 12
key_code<1> XXXXX.............X..X.................. 7
key_code<0> XXXXX............X...X.................. 7
div_cnt<5> X....X.X.XXX.........X.................. 7
dataout<6> .................XXXX................... 4
key_code<3> XXXXX...X...........XX.................. 8
div_cnt<9> X....X.X.XXXXXXX.....X.................. 11
0----+----1----+----2----+----3----+----4
0 0 0 0
******************************* Equations ********************************
********** Mapped Logic **********
dataout(0) <= '1';
dataout(1) <= ((NOT key_code(1) AND NOT key_code(2) AND NOT key_code(3))
OR (key_code(1) AND key_code(0) AND key_code(2) AND
NOT key_code(3))
OR (NOT key_code(1) AND NOT key_code(0) AND key_code(2) AND
key_code(3)));
dataout(2) <= ((key_code(1) AND key_code(0) AND NOT key_code(3))
OR (key_code(1) AND NOT key_code(2) AND NOT key_code(3))
OR (key_code(0) AND NOT key_code(2) AND NOT key_code(3))
OR (NOT key_code(1) AND key_code(0) AND key_code(2) AND
key_code(3)));
dataout(3) <= ((key_code(0) AND NOT key_code(3))
OR (NOT key_code(1) AND key_code(0) AND NOT key_code(2))
OR (NOT key_code(1) AND key_code(2) AND NOT key_code(3)));
dataout(4) <= ((key_code(1) AND key_code(0) AND key_code(2))
OR (NOT key_code(1) AND key_code(0) AND NOT key_code(2))
OR (key_code(1) AND NOT key_code(0) AND NOT key_code(2) AND
key_code(3))
OR (NOT key_code(1) AND NOT key_code(0) AND key_code(2) AND
NOT key_code(3)));
dataout(5) <= ((key_code(1) AND key_code(2) AND key_code(3))
OR (NOT key_code(0) AND key_code(2) AND key_code(3))
OR (key_code(1) AND NOT key_code(0) AND NOT key_code(2) AND
NOT key_code(3)));
dataout(6) <= ((div_cnt(5).EXP)
OR (key_code(1) AND key_code(0) AND key_code(3))
OR (key_code(1) AND NOT key_code(0) AND key_code(2)));
dataout(7) <= ((key_code(1) AND key_code(0) AND NOT key_code(2) AND
key_code(3))
OR (NOT key_code(1) AND key_code(0) AND key_code(2) AND
key_code(3))
OR (NOT key_code(1) AND key_code(0) AND NOT key_code(2) AND
NOT key_code(3))
OR (NOT key_code(1) AND NOT key_code(0) AND key_code(2) AND
NOT key_code(3)));
FTCPE_div_cnt0: FTCPE port map (div_cnt(0),'1',clk,NOT rst,'0');
FTCPE_div_cnt1: FTCPE port map (div_cnt(1),div_cnt(0),clk,NOT rst,'0');
FTCPE_div_cnt2: FTCPE port map (div_cnt(2),div_cnt_T(2),clk,NOT rst,'0');
div_cnt_T(2) <= (div_cnt(0) AND div_cnt(1));
FTCPE_div_cnt3: FTCPE port map (div_cnt(3),div_cnt_T(3),clk,NOT rst,'0');
div_cnt_T(3) <= (div_cnt(0) AND div_cnt(1) AND div_cnt(2));
FTCPE_div_cnt4: FTCPE port map (div_cnt(4),div_cnt_T(4),clk,NOT rst,'0');
div_cnt_T(4) <= (div_cnt(0) AND div_cnt(1) AND div_cnt(2) AND
div_cnt(3));
FTCPE_div_cnt5: FTCPE port map (div_cnt(5),div_cnt_T(5),clk,NOT rst,'0');
div_cnt_T(5) <= (div_cnt(0) AND div_cnt(1) AND div_cnt(2) AND
div_cnt(3) AND div_cnt(4));
FTCPE_div_cnt6: FTCPE port map (div_cnt(6),div_cnt_T(6),clk,NOT rst,'0');
div_cnt_T(6) <= (div_cnt(0) AND div_cnt(1) AND div_cnt(2) AND
div_cnt(3) AND div_cnt(4) AND div_cnt(5));
FTCPE_div_cnt7: FTCPE port map (div_cnt(7),div_cnt_T(7),clk,NOT rst,'0');
div_cnt_T(7) <= (div_cnt(0) AND div_cnt(1) AND div_cnt(2) AND
div_cnt(3) AND div_cnt(4) AND div_cnt(5) AND div_cnt(6));
FTCPE_div_cnt8: FTCPE port map (div_cnt(8),div_cnt_T(8),clk,NOT rst,'0');
div_cnt_T(8) <= (div_cnt(0) AND div_cnt(1) AND div_cnt(2) AND
div_cnt(3) AND div_cnt(4) AND div_cnt(5) AND div_cnt(6) AND
div_cnt(7));
FTCPE_div_cnt9: FTCPE port map (div_cnt(9),div_cnt_T(9),clk,NOT rst,'0');
div_cnt_T(9) <= (div_cnt(0) AND div_cnt(1) AND div_cnt(2) AND
div_cnt(3) AND div_cnt(4) AND div_cnt(5) AND div_cnt(6) AND
div_cnt(7) AND div_cnt(8));
FTCPE_div_cnt10: FTCPE port map (div_cnt(10),div_cnt_T(10),clk,NOT rst,'0');
div_cnt_T(10) <= (div_cnt(0) AND div_cnt(1) AND div_cnt(2) AND
div_cnt(3) AND div_cnt(4) AND div_cnt(5) AND div_cnt(6) AND
div_cnt(7) AND div_cnt(8) AND div_cnt(9));
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