keyscan.rpt
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RPT
772 行
cpldfit: version H.42 Xilinx Inc.
Fitter Report
Design Name: keyscan Date: 2-21-2006, 10:57AM
Device Used: XC95144XL-10-TQ144
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
45 /144 ( 31%) 123 /720 ( 17%) 70 /432 ( 16%) 25 /144 ( 17%) 26 /117 ( 22%)
** Function Block Resources **
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 4/18 22/54 12/90 0/15
FB2 0/18 0/54 0/90 0/15
FB3 0/18 0/54 0/90 0/15
FB4 14/18 22/54 26/90 6/15
FB5 0/18 0/54 0/90 0/14
FB6 9/18 4/54 18/90 9/13
FB7 0/18 0/54 0/90 0/15
FB8 18/18* 22/54 67/90 5/15
----- ----- ----- -----
45/144 70/432 123/720 20/117
* - Resource is exhausted
** Global Control Resources **
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 6 6 | I/O : 26 109
Output : 20 20 | GCK/IO : 0 3
Bidirectional : 0 0 | GTS/IO : 0 4
GCK : 0 0 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 26 26
** Power Data **
There are 45 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
************************* Summary of Mapped Logic ************************
** 20 Outputs **
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
dataout<1> 3 4 FB4_1 118 I/O O STD FAST
en<2> 0 0 FB4_2 126 I/O O STD FAST
en<6> 0 0 FB4_3 133 I/O O STD FAST
en<0> 0 0 FB4_9 131 I/O O STD FAST
en<1> 0 0 FB4_11 132 I/O O STD FAST
en<7> 0 0 FB4_12 134 I/O O STD FAST
dataout<7> 4 4 FB6_2 106 I/O O STD FAST
dataout<5> 3 4 FB6_4 111 I/O O STD FAST
dataout<4> 4 4 FB6_8 113 I/O O STD FAST
dataout<2> 4 4 FB6_9 116 I/O O STD FAST
dataout<3> 3 4 FB6_10 115 I/O O STD FAST
dataout<0> 0 0 FB6_11 119 I/O O STD FAST
en<3> 0 0 FB6_12 120 I/O O STD FAST
en<4> 0 0 FB6_15 124 I/O O STD FAST
en<5> 0 0 FB6_17 125 I/O O STD FAST
row<3> 1 2 FB8_2 91 I/O O STD FAST
row<2> 1 2 FB8_5 92 I/O O STD FAST
row<1> 1 2 FB8_6 93 I/O O STD FAST
row<0> 1 2 FB8_8 94 I/O O STD FAST
dataout<6> 4 4 FB8_16 107 I/O O STD FAST
** 25 Buried Nodes **
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
div_cnt<20> 3 22 FB1_15 STD RESET
div_cnt<19> 3 21 FB1_16 STD RESET
div_cnt<18> 3 20 FB1_17 STD RESET
div_cnt<17> 3 19 FB1_18 STD RESET
div_cnt<0> 2 2 FB4_8 STD RESET
div_cnt<1> 3 3 FB4_10 STD RESET
div_cnt<16> 3 18 FB4_13 STD RESET
div_cnt<15> 3 17 FB4_14 STD RESET
div_cnt<14> 3 16 FB4_15 STD RESET
div_cnt<13> 3 15 FB4_16 STD RESET
div_cnt<12> 3 14 FB4_17 STD RESET
div_cnt<11> 3 13 FB4_18 STD RESET
key_code<2> 10 8 FB8_1 STD RESET
div_cnt<7> 3 9 FB8_3 STD RESET
div_cnt<8> 3 10 FB8_4 STD RESET
div_cnt<6> 3 8 FB8_7 STD RESET
div_cnt<3> 3 5 FB8_9 STD RESET
div_cnt<4> 3 6 FB8_10 STD RESET
div_cnt<2> 3 4 FB8_11 STD RESET
div_cnt<10> 3 12 FB8_12 STD RESET
key_code<1> 6 7 FB8_13 STD RESET
key_code<0> 6 7 FB8_14 STD RESET
div_cnt<5> 3 7 FB8_15 STD RESET
key_code<3> 10 8 FB8_17 STD RESET
div_cnt<9> 3 11 FB8_18 STD RESET
** 6 Inputs **
Signal Loc Pin Pin Pin
Name No. Type Use
clk FB4_5 128 I/O I
rst FB7_2 71 I/O I
column<2> FB8_4 97 I/O I
column<3> FB8_9 96 I/O I
column<1> FB8_11 98 I/O I
column<0> FB8_12 100 I/O I
Legend:
Pin No. - ~ - User Assigned
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X - Signal used as input to the macrocell logic.
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 22/32
Number of signals used by logic mapping into function block: 22
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB1_1 23 I/O
(unused) 0 0 0 5 FB1_2 16 I/O
(unused) 0 0 0 5 FB1_3 17 I/O
(unused) 0 0 0 5 FB1_4 25 I/O
(unused) 0 0 0 5 FB1_5 19 I/O
(unused) 0 0 0 5 FB1_6 20 I/O
(unused) 0 0 0 5 FB1_7 (b)
(unused) 0 0 0 5 FB1_8 21 I/O
(unused) 0 0 0 5 FB1_9 22 I/O
(unused) 0 0 0 5 FB1_10 31 I/O
(unused) 0 0 0 5 FB1_11 24 I/O
(unused) 0 0 0 5 FB1_12 26 I/O
(unused) 0 0 0 5 FB1_13 (b)
(unused) 0 0 0 5 FB1_14 27 I/O
div_cnt<20> 3 0 0 2 FB1_15 28 I/O (b)
div_cnt<19> 3 0 0 2 FB1_16 35 I/O (b)
div_cnt<18> 3 0 0 2 FB1_17 30 GCK/I/O (b)
div_cnt<17> 3 0 0 2 FB1_18 (b) (b)
Signals Used by Logic in Function Block
1: clk 9: div_cnt<16> 16: div_cnt<4>
2: div_cnt<0> 10: div_cnt<17> 17: div_cnt<5>
3: div_cnt<10> 11: div_cnt<18> 18: div_cnt<6>
4: div_cnt<11> 12: div_cnt<19> 19: div_cnt<7>
5: div_cnt<12> 13: div_cnt<1> 20: div_cnt<8>
6: div_cnt<13> 14: div_cnt<2> 21: div_cnt<9>
7: div_cnt<14> 15: div_cnt<3> 22: rst
8: div_cnt<15>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
div_cnt<20> XXXXXXXXXXXXXXXXXXXXXX.................. 22
div_cnt<19> XXXXXXXXXXX.XXXXXXXXXX.................. 21
div_cnt<18> XXXXXXXXXX..XXXXXXXXXX.................. 20
div_cnt<17> XXXXXXXXX...XXXXXXXXXX.................. 19
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 0/54
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB2_1 142 I/O
(unused) 0 0 0 5 FB2_2 143 GSR/I/O
(unused) 0 0 0 5 FB2_3 (b)
(unused) 0 0 0 5 FB2_4 4 I/O
(unused) 0 0 0 5 FB2_5 2 GTS/I/O
(unused) 0 0 0 5 FB2_6 3 GTS/I/O
(unused) 0 0 0 5 FB2_7 (b)
(unused) 0 0 0 5 FB2_8 5 GTS/I/O
(unused) 0 0 0 5 FB2_9 6 GTS/I/O
(unused) 0 0 0 5 FB2_10 7 I/O
(unused) 0 0 0 5 FB2_11 9 I/O
(unused) 0 0 0 5 FB2_12 10 I/O
(unused) 0 0 0 5 FB2_13 12 I/O
(unused) 0 0 0 5 FB2_14 11 I/O
(unused) 0 0 0 5 FB2_15 13 I/O
(unused) 0 0 0 5 FB2_16 14 I/O
(unused) 0 0 0 5 FB2_17 15 I/O
(unused) 0 0 0 5 FB2_18 (b)
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 0/54
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB3_1 39 I/O
(unused) 0 0 0 5 FB3_2 32 GCK/I/O
(unused) 0 0 0 5 FB3_3 41 I/O
(unused) 0 0 0 5 FB3_4 44 I/O
(unused) 0 0 0 5 FB3_5 33 I/O
(unused) 0 0 0 5 FB3_6 34 I/O
(unused) 0 0 0 5 FB3_7 46 I/O
(unused) 0 0 0 5 FB3_8 38 GCK/I/O
(unused) 0 0 0 5 FB3_9 40 I/O
(unused) 0 0 0 5 FB3_10 48 I/O
(unused) 0 0 0 5 FB3_11 43 I/O
(unused) 0 0 0 5 FB3_12 45 I/O
(unused) 0 0 0 5 FB3_13 (b)
(unused) 0 0 0 5 FB3_14 49 I/O
(unused) 0 0 0 5 FB3_15 50 I/O
(unused) 0 0 0 5 FB3_16 (b)
(unused) 0 0 0 5 FB3_17 51 I/O
(unused) 0 0 0 5 FB3_18 (b)
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 22/32
Number of signals used by logic mapping into function block: 22
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
dataout<1> 3 0 0 2 FB4_1 118 I/O O
en<2> 0 0 0 5 FB4_2 126 I/O O
en<6> 0 0 0 5 FB4_3 133 I/O O
(unused) 0 0 0 5 FB4_4 (b)
(unused) 0 0 0 5 FB4_5 128 I/O I
(unused) 0 0 0 5 FB4_6 129 I/O
(unused) 0 0 0 5 FB4_7 (b)
div_cnt<0> 2 0 0 3 FB4_8 130 I/O (b)
en<0> 0 0 0 5 FB4_9 131 I/O O
div_cnt<1> 3 0 0 2 FB4_10 135 I/O (b)
en<1> 0 0 0 5 FB4_11 132 I/O O
en<7> 0 0 0 5 FB4_12 134 I/O O
div_cnt<16> 3 0 0 2 FB4_13 137 I/O (b)
div_cnt<15> 3 0 0 2 FB4_14 136 I/O (b)
div_cnt<14> 3 0 0 2 FB4_15 138 I/O (b)
div_cnt<13> 3 0 0 2 FB4_16 139 I/O (b)
div_cnt<12> 3 0 0 2 FB4_17 140 I/O (b)
div_cnt<11> 3 0 0 2 FB4_18 (b) (b)
Signals Used by Logic in Function Block
1: clk 9: div_cnt<1> 16: div_cnt<8>
2: div_cnt<0> 10: div_cnt<2> 17: div_cnt<9>
3: div_cnt<10> 11: div_cnt<3> 18: key_code<0>
4: div_cnt<11> 12: div_cnt<4> 19: key_code<1>
5: div_cnt<12> 13: div_cnt<5> 20: key_code<2>
6: div_cnt<13> 14: div_cnt<6> 21: key_code<3>
7: div_cnt<14> 15: div_cnt<7> 22: rst
8: div_cnt<15>
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