keyscan.twr

来自「Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档」· TWR 代码 · 共 74 行

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Release 7.1i Trace H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

D:/Xilinx/bin/nt/trce.exe -ise
e:\temp\spartan2\vhdl\interface\keyscan\KeyScan.ise -intstyle ise -e 3 -l 3 -s
6 -xml keyscan keyscan.ncd -o keyscan.twr keyscan.pcf


Design file:              keyscan.ncd
Physical constraint file: keyscan.pcf
Device,speed:             xc2s50,-6 (PRODUCTION 1.27 2005-01-22)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clk
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
column<0>   |    4.337(R)|   -1.529(R)|clk_BUFGP         |   0.000|
column<1>   |    4.517(R)|   -1.714(R)|clk_BUFGP         |   0.000|
column<2>   |    4.353(R)|   -1.305(R)|clk_BUFGP         |   0.000|
column<3>   |    3.977(R)|   -1.482(R)|clk_BUFGP         |   0.000|
------------+------------+------------+------------------+--------+

Clock clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
dataout<0>  |   13.010(R)|clk_BUFGP         |   0.000|
dataout<1>  |   11.193(R)|clk_BUFGP         |   0.000|
dataout<2>  |   11.286(R)|clk_BUFGP         |   0.000|
dataout<3>  |   11.109(R)|clk_BUFGP         |   0.000|
dataout<4>  |   10.980(R)|clk_BUFGP         |   0.000|
dataout<5>  |   10.848(R)|clk_BUFGP         |   0.000|
dataout<6>  |   10.776(R)|clk_BUFGP         |   0.000|
dataout<7>  |   10.487(R)|clk_BUFGP         |   0.000|
row<0>      |   10.680(R)|clk_BUFGP         |   0.000|
row<1>      |    9.950(R)|clk_BUFGP         |   0.000|
row<2>      |   11.023(R)|clk_BUFGP         |   0.000|
row<3>      |   10.017(R)|clk_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    7.040|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Tue Mar 14 15:00:45 2006
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Peak Memory Usage: 62 MB