📄 state_machine.rpt
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cnt<12> 3 0 0 2 FB4_18 (b) (b)
Signals Used by Logic in Function Block
1: clk 11: cnt<18> 20: cnt<5>
2: cnt<0> 12: cnt<19> 21: cnt<6>
3: cnt<10> 13: cnt<1> 22: cnt<7>
4: cnt<11> 14: cnt<20> 23: cnt<8>
5: cnt<12> 15: cnt<21> 24: cnt<9>
6: cnt<13> 16: cnt<22> 25: rst
7: cnt<14> 17: cnt<2> 26: state_FFd1
8: cnt<15> 18: cnt<3> 27: state_FFd2
9: cnt<16> 19: cnt<4> 28: state_FFd3
10: cnt<17>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
c<1> .........................XXX............ 3
en<5> ........................................ 0
en<1> ........................................ 0
cnt<23> XXXXXXXXXXXXXXXXXXXXXXXXX............... 25
cnt<22> XXXXXXXXXXXXXXX.XXXXXXXXX............... 24
cnt<21> XXXXXXXXXXXXXX..XXXXXXXXX............... 23
cnt<20> XXXXXXXXXXXXX...XXXXXXXXX............... 22
cnt<19> XXXXXXXXXXX.X...XXXXXXXXX............... 21
en<6> ........................................ 0
cnt<18> XXXXXXXXXX..X...XXXXXXXXX............... 20
en<7> ........................................ 0
en<0> ........................................ 0
cnt<17> XXXXXXXXX...X...XXXXXXXXX............... 19
cnt<16> XXXXXXXX....X...XXXXXXXXX............... 18
cnt<15> XXXXXXX.....X...XXXXXXXXX............... 17
cnt<14> XXXXXX......X...XXXXXXXXX............... 16
cnt<13> XXXXX.......X...XXXXXXXXX............... 15
cnt<12> XXXX........X...XXXXXXXXX............... 14
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB5 ***********************************
Number of function block inputs used/remaining: 0/54
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB5_1 (b)
(unused) 0 0 0 5 FB5_2 52 I/O
(unused) 0 0 0 5 FB5_3 59 I/O
(unused) 0 0 0 5 FB5_4 (b)
(unused) 0 0 0 5 FB5_5 53 I/O
(unused) 0 0 0 5 FB5_6 54 I/O
(unused) 0 0 0 5 FB5_7 66 I/O
(unused) 0 0 0 5 FB5_8 56 I/O
(unused) 0 0 0 5 FB5_9 57 I/O
(unused) 0 0 0 5 FB5_10 68 I/O
(unused) 0 0 0 5 FB5_11 58 I/O
(unused) 0 0 0 5 FB5_12 60 I/O
(unused) 0 0 0 5 FB5_13 70 I/O
(unused) 0 0 0 5 FB5_14 61 I/O
(unused) 0 0 0 5 FB5_15 64 I/O
(unused) 0 0 0 5 FB5_16 (b)
(unused) 0 0 0 5 FB5_17 69 I/O
(unused) 0 0 0 5 FB5_18 (b)
*********************************** FB6 ***********************************
Number of function block inputs used/remaining: 16/38
Number of signals used by logic mapping into function block: 16
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
cnt<9> 3 0 0 2 FB6_1 (b) (b)
c<7> 2 0 0 3 FB6_2 106 I/O O
cnt<8> 3 0 0 2 FB6_3 (b) (b)
c<5> 1 0 0 4 FB6_4 111 I/O O
cnt<7> 3 0 0 2 FB6_5 110 I/O (b)
cnt<6> 3 0 0 2 FB6_6 112 I/O (b)
cnt<5> 3 0 0 2 FB6_7 (b) (b)
c<4> 3 0 0 2 FB6_8 113 I/O O
c<2> 3 0 0 2 FB6_9 116 I/O O
c<3> 2 0 0 3 FB6_10 115 I/O O
c<0> 0 0 0 5 FB6_11 119 I/O O
en<4> 0 0 0 5 FB6_12 120 I/O O
cnt<4> 3 0 0 2 FB6_13 (b) (b)
cnt<3> 3 0 0 2 FB6_14 121 I/O (b)
en<3> 0 0 0 5 FB6_15 124 I/O O
cnt<11> 3 0 0 2 FB6_16 117 I/O (b)
en<2> 0 0 0 5 FB6_17 125 I/O O
cnt<10> 3 0 0 2 FB6_18 (b) (b)
Signals Used by Logic in Function Block
1: clk 7: cnt<4> 12: cnt<9>
2: cnt<0> 8: cnt<5> 13: rst
3: cnt<10> 9: cnt<6> 14: state_FFd1
4: cnt<1> 10: cnt<7> 15: state_FFd2
5: cnt<2> 11: cnt<8> 16: state_FFd3
6: cnt<3>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
cnt<9> XX.XXXXXXXX.X........................... 11
c<7> .............XXX........................ 3
cnt<8> XX.XXXXXXX..X........................... 10
c<5> .............XXX........................ 3
cnt<7> XX.XXXXXX...X........................... 9
cnt<6> XX.XXXXX....X........................... 8
cnt<5> XX.XXXX.....X........................... 7
c<4> .............XXX........................ 3
c<2> .............XXX........................ 3
c<3> .............XXX........................ 3
c<0> ........................................ 0
en<4> ........................................ 0
cnt<4> XX.XXX......X........................... 6
cnt<3> XX.XX.......X........................... 5
en<3> ........................................ 0
cnt<11> XXXXXXXXXXXXX........................... 13
en<2> ........................................ 0
cnt<10> XX.XXXXXXXXXX........................... 12
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB7 ***********************************
Number of function block inputs used/remaining: 0/54
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB7_1 (b)
(unused) 0 0 0 5 FB7_2 71 I/O I
(unused) 0 0 0 5 FB7_3 75 I/O
(unused) 0 0 0 5 FB7_4 (b)
(unused) 0 0 0 5 FB7_5 74 I/O
(unused) 0 0 0 5 FB7_6 76 I/O
(unused) 0 0 0 5 FB7_7 77 I/O
(unused) 0 0 0 5 FB7_8 78 I/O
(unused) 0 0 0 5 FB7_9 80 I/O
(unused) 0 0 0 5 FB7_10 79 I/O
(unused) 0 0 0 5 FB7_11 82 I/O
(unused) 0 0 0 5 FB7_12 85 I/O
(unused) 0 0 0 5 FB7_13 81 I/O
(unused) 0 0 0 5 FB7_14 86 I/O
(unused) 0 0 0 5 FB7_15 87 I/O
(unused) 0 0 0 5 FB7_16 83 I/O
(unused) 0 0 0 5 FB7_17 88 I/O
(unused) 0 0 0 5 FB7_18 (b)
*********************************** FB8 ***********************************
Number of function block inputs used/remaining: 7/47
Number of signals used by logic mapping into function block: 7
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB8_1 (b)
(unused) 0 0 0 5 FB8_2 91 I/O
(unused) 0 0 0 5 FB8_3 95 I/O
(unused) 0 0 0 5 FB8_4 97 I/O
(unused) 0 0 0 5 FB8_5 92 I/O
(unused) 0 0 0 5 FB8_6 93 I/O
(unused) 0 0 0 5 FB8_7 (b)
(unused) 0 0 0 5 FB8_8 94 I/O
(unused) 0 0 0 5 FB8_9 96 I/O
(unused) 0 0 0 5 FB8_10 101 I/O
(unused) 0 0 0 5 FB8_11 98 I/O
(unused) 0 0 0 5 FB8_12 100 I/O
(unused) 0 0 0 5 FB8_13 103 I/O
(unused) 0 0 0 5 FB8_14 102 I/O
cnt<0> 2 0 0 3 FB8_15 104 I/O (b)
c<6> 2 0 0 3 FB8_16 107 I/O O
cnt<2> 3 0 0 2 FB8_17 105 I/O (b)
cnt<1> 3 0 0 2 FB8_18 (b) (b)
Signals Used by Logic in Function Block
1: clk 4: rst 6: state_FFd2
2: cnt<0> 5: state_FFd1 7: state_FFd3
3: cnt<1>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
cnt<0> X..X.................................... 2
c<6> ....XXX................................. 3
cnt<2> XXXX.................................... 4
cnt<1> XX.X.................................... 3
0----+----1----+----2----+----3----+----4
0 0 0 0
******************************* Equations ********************************
********** Mapped Logic **********
c(0) <= '1';
c(1) <= ((NOT state_FFd2 AND NOT state_FFd1)
OR (state_FFd2 AND state_FFd3 AND state_FFd1));
c(2) <= ((state_FFd2 AND state_FFd3)
OR (state_FFd2 AND NOT state_FFd1)
OR (state_FFd3 AND NOT state_FFd1));
c(3) <= ((state_FFd3)
OR (NOT state_FFd2 AND state_FFd1));
c(4) <= ((state_FFd2 AND state_FFd3 AND state_FFd1)
OR (NOT state_FFd2 AND state_FFd3 AND NOT state_FFd1)
OR (NOT state_FFd2 AND NOT state_FFd3 AND state_FFd1));
c(5) <= (state_FFd2 AND NOT state_FFd3 AND NOT state_FFd1);
c(6) <= ((state_FFd2 AND NOT state_FFd3 AND state_FFd1)
OR (NOT state_FFd2 AND state_FFd3 AND state_FFd1));
c(7) <= ((NOT state_FFd2 AND state_FFd3 AND NOT state_FFd1)
OR (NOT state_FFd2 AND NOT state_FFd3 AND state_FFd1));
FTCPE_cnt0: FTCPE port map (cnt(0),'1',clk,NOT rst,'0');
FTCPE_cnt1: FTCPE port map (cnt(1),cnt(0),clk,NOT rst,'0');
FTCPE_cnt2: FTCPE port map (cnt(2),cnt_T(2),clk,NOT rst,'0');
cnt_T(2) <= (cnt(0) AND cnt(1));
FTCPE_cnt3: FTCPE port map (cnt(3),cnt_T(3),clk,NOT rst,'0');
cnt_T(3) <= (cnt(0) AND cnt(1) AND cnt(2));
FTCPE_cnt4: FTCPE port map (cnt(4),cnt_T(4),clk,NOT rst,'0');
cnt_T(4) <= (cnt(0) AND cnt(1) AND cnt(2) AND cnt(3));
FTCPE_cnt5: FTCPE port map (cnt(5),cnt_T(5),clk,NOT rst,'0');
cnt_T(5) <= (cnt(0) AND cnt(1) AND cnt(2) AND cnt(3) AND cnt(4));
FTCPE_cnt6: FTCPE port map (cnt(6),cnt_T(6),clk,NOT rst,'0');
cnt_T(6) <= (cnt(0) AND cnt(1) AND cnt(2) AND cnt(3) AND cnt(4) AND
cnt(5));
FTCPE_cnt7: FTCPE port map (cnt(7),cnt_T(7),clk,NOT rst,'0');
cnt_T(7) <= (cnt(0) AND cnt(1) AND cnt(2) AND cnt(3) AND cnt(4) AND
cnt(5) AND cnt(6));
FTCPE_cnt8: FTCPE port map (cnt(8),cnt_T(8),clk,NOT rst,'0');
cnt_T(8) <= (cnt(0) AND cnt(1) AND cnt(2) AND cnt(3) AND cnt(4) AND
cnt(5) AND cnt(6) AND cnt(7));
FTCPE_cnt9: FTCPE port map (cnt(9),cnt_T(9),clk,NOT rst,'0');
cnt_T(9) <= (cnt(0) AND cnt(1) AND cnt(2) AND cnt(3) AND cnt(4) AND
cnt(5) AND cnt(6) AND cnt(7) AND cnt(8));
FTCPE_cnt10: FTCPE port map (cnt(10),cnt_T(10),clk,NOT rst,'0');
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