sub.rpt
来自「Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档」· RPT 代码 · 共 755 行 · 第 1/3 页
RPT
755 行
cpldfit: version H.42 Xilinx Inc.
Fitter Report
Design Name: sub Date: 2-21-2006, 1:01PM
Device Used: XC95144XL-10-TQ144
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
25 /144 ( 17%) 170 /720 ( 24%) 50 /432 ( 12%) 0 /144 ( 0%) 24 /117 ( 21%)
** Function Block Resources **
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 5/18 9/54 77/90 0/15
FB2 1/18 8/54 23/90 0/15
FB3 1/18 2/54 2/90 0/15
FB4 6/18 12/54 18/90 6/15
FB5 0/18 0/54 0/90 0/14
FB6 9/18 11/54 23/90 9/13
FB7 0/18 0/54 0/90 0/15
FB8 3/18 8/54 27/90 1/15
----- ----- ----- -----
25/144 50/432 170/720 16/117
* - Resource is exhausted
** Global Control Resources **
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 8 8 | I/O : 24 109
Output : 16 16 | GCK/IO : 0 3
Bidirectional : 0 0 | GTS/IO : 0 4
GCK : 0 0 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 24 24
** Power Data **
There are 25 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
************************** Errors and Warnings ***************************
WARNING:Cpld:896 - Unable to map all desired signals into function block, FB6,
because too many function block product terms are required. Buffering output
signal c<5> to allow all signals assigned to this function block to be
placed.
WARNING:Cpld:896 - Unable to map all desired signals into function block, FB6,
because too many function block product terms are required. Buffering output
signal c<2> to allow all signals assigned to this function block to be
placed.
WARNING:Cpld:896 - Unable to map all desired signals into function block, FB6,
because too many function block product terms are required. Buffering output
signal c<4> to allow all signals assigned to this function block to be
placed.
WARNING:Cpld:896 - Unable to map all desired signals into function block, FB6,
because too many function block product terms are required. Buffering output
signal c<3> to allow all signals assigned to this function block to be
placed.
************************* Summary of Mapped Logic ************************
** 16 Outputs **
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
c<1> 17 12 FB4_1 118 I/O O STD FAST
en<5> 1 0 FB4_2 126 I/O O STD FAST
en<1> 0 0 FB4_3 133 I/O O STD FAST
en<6> 0 0 FB4_9 131 I/O O STD FAST
en<7> 0 0 FB4_11 132 I/O O STD FAST
en<0> 0 0 FB4_12 134 I/O O STD FAST
c<7> 19 9 FB6_2 106 I/O O STD FAST
c<5> 1 1 FB6_4 111 I/O O STD FAST
c<4> 1 1 FB6_8 113 I/O O STD FAST
c<2> 1 1 FB6_9 116 I/O O STD FAST
c<3> 1 1 FB6_10 115 I/O O STD FAST
c<0> 0 0 FB6_11 119 I/O O STD FAST
en<4> 0 0 FB6_12 120 I/O O STD FAST
en<3> 0 0 FB6_15 124 I/O O STD FAST
en<2> 0 0 FB6_17 125 I/O O STD FAST
c<6> 22 8 FB8_16 107 I/O O STD FAST
** 9 Buried Nodes **
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
c<3>_BUFR 20 7 FB1_3 STD
Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D 2 2 FB1_5 STD
c<5>_BUFR 24 9 FB1_8 STD
Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 7 6 FB1_14 STD
c<2>_BUFR 24 7 FB1_16 STD
c<4>_BUFR 23 8 FB2_16 STD
Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D 2 2 FB3_18 STD
$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 3 4 FB8_1 STD
Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D 2 2 FB8_18 STD
** 8 Inputs **
Signal Loc Pin Pin Pin
Name No. Type Use
b<0> FB5_3 59 I/O I
a<1> FB5_7 66 I/O I
b<3> FB5_8 56 I/O I
b<2> FB5_9 57 I/O I
b<1> FB5_11 58 I/O I
a<3> FB5_14 61 I/O I
a<2> FB5_15 64 I/O I
a<0> FB5_17 69 I/O I
Legend:
Pin No. - ~ - User Assigned
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X - Signal used as input to the macrocell logic.
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 9/45
Number of signals used by logic mapping into function block: 9
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 \/5 0 FB1_1 23 I/O (b)
(unused) 0 0 \/5 0 FB1_2 16 I/O (b)
c<3>_BUFR 20 15<- 0 0 FB1_3 17 I/O (b)
(unused) 0 0 /\5 0 FB1_4 25 I/O (b)
Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
2 0 0 3 FB1_5 19 I/O (b)
(unused) 0 0 \/4 1 FB1_6 20 I/O (b)
(unused) 0 0 \/5 0 FB1_7 (b) (b)
c<5>_BUFR 24 19<- 0 0 FB1_8 21 I/O (b)
(unused) 0 0 /\5 0 FB1_9 22 I/O (b)
(unused) 0 0 /\5 0 FB1_10 31 I/O (b)
(unused) 0 0 0 5 FB1_11 24 I/O
(unused) 0 0 \/1 4 FB1_12 26 I/O (b)
(unused) 0 0 \/5 0 FB1_13 (b) (b)
Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2
7 6<- \/4 0 FB1_14 27 I/O (b)
(unused) 0 0 \/5 0 FB1_15 28 I/O (b)
c<2>_BUFR 24 19<- 0 0 FB1_16 35 I/O (b)
(unused) 0 0 /\5 0 FB1_17 30 GCK/I/O (b)
(unused) 0 0 /\5 0 FB1_18 (b) (b)
Signals Used by Logic in Function Block
1: Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D 4: a<1> 7: b<1>
2: Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 5: a<2> 8: b<2>
3: a<0> 6: b<0> 9: c<3>_BUFR
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
c<3>_BUFR X.XXXXXX................................ 7
Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
....X..X................................ 2
c<5>_BUFR XXXXXXXXX............................... 9
Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2
..XXXXXX................................ 6
c<2>_BUFR X.XXXXXX................................ 7
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 8/46
Number of signals used by logic mapping into function block: 8
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB2_1 142 I/O
(unused) 0 0 0 5 FB2_2 143 GSR/I/O
(unused) 0 0 0 5 FB2_3 (b)
(unused) 0 0 0 5 FB2_4 4 I/O
(unused) 0 0 0 5 FB2_5 2 GTS/I/O
(unused) 0 0 0 5 FB2_6 3 GTS/I/O
(unused) 0 0 0 5 FB2_7 (b)
(unused) 0 0 0 5 FB2_8 5 GTS/I/O
(unused) 0 0 0 5 FB2_9 6 GTS/I/O
(unused) 0 0 0 5 FB2_10 7 I/O
(unused) 0 0 0 5 FB2_11 9 I/O
(unused) 0 0 0 5 FB2_12 10 I/O
(unused) 0 0 0 5 FB2_13 12 I/O
(unused) 0 0 \/3 2 FB2_14 11 I/O (b)
(unused) 0 0 \/5 0 FB2_15 13 I/O (b)
c<4>_BUFR 23 18<- 0 0 FB2_16 14 I/O (b)
(unused) 0 0 /\5 0 FB2_17 15 I/O (b)
(unused) 0 0 /\5 0 FB2_18 (b) (b)
Signals Used by Logic in Function Block
1: Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D 4: a<1> 7: b<1>
2: Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D 5: a<2> 8: b<2>
3: a<0> 6: b<0>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
c<4>_BUFR XXXXXXXX................................ 8
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 2/52
Number of signals used by logic mapping into function block: 2
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB3_1 39 I/O
(unused) 0 0 0 5 FB3_2 32 GCK/I/O
(unused) 0 0 0 5 FB3_3 41 I/O
(unused) 0 0 0 5 FB3_4 44 I/O
(unused) 0 0 0 5 FB3_5 33 I/O
(unused) 0 0 0 5 FB3_6 34 I/O
(unused) 0 0 0 5 FB3_7 46 I/O
(unused) 0 0 0 5 FB3_8 38 GCK/I/O
(unused) 0 0 0 5 FB3_9 40 I/O
(unused) 0 0 0 5 FB3_10 48 I/O
(unused) 0 0 0 5 FB3_11 43 I/O
(unused) 0 0 0 5 FB3_12 45 I/O
(unused) 0 0 0 5 FB3_13 (b)
(unused) 0 0 0 5 FB3_14 49 I/O
(unused) 0 0 0 5 FB3_15 50 I/O
(unused) 0 0 0 5 FB3_16 (b)
(unused) 0 0 0 5 FB3_17 51 I/O
Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
2 0 0 3 FB3_18 (b) (b)
Signals Used by Logic in Function Block
1: a<3> 2: b<3>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
XX...................................... 2
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 12/42
Number of signals used by logic mapping into function block: 12
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
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