bcd.twr

来自「Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档」· TWR 代码 · 共 93 行

TWR
93
字号
--------------------------------------------------------------------------------
Release 7.1i Trace H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

D:/Xilinx/bin/nt/trce.exe -ise e:\temp\spartan2\vhdl\basic\bcd\BCD.ise
-intstyle ise -e 3 -l 3 -s 6 -xml bcd bcd.ncd -o bcd.twr bcd.pcf


Design file:              bcd.ncd
Physical constraint file: bcd.pcf
Device,speed:             xc2s50,-6 (PRODUCTION 1.27 2005-01-22)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
c<1>        |   13.249(F)|clk_BUFGP         |   0.000|
c<2>        |   13.820(F)|clk_BUFGP         |   0.000|
c<3>        |   13.805(F)|clk_BUFGP         |   0.000|
c<4>        |   14.074(F)|clk_BUFGP         |   0.000|
c<5>        |   14.387(F)|clk_BUFGP         |   0.000|
c<6>        |   13.981(F)|clk_BUFGP         |   0.000|
c<7>        |   14.438(F)|clk_BUFGP         |   0.000|
en<0>       |    9.044(F)|clk_BUFGP         |   0.000|
en<1>       |    8.819(F)|clk_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |         |         |         |    9.215|
---------------+---------+---------+---------+---------+

Pad to Pad
---------------+---------------+---------+
Source Pad     |Destination Pad|  Delay  |
---------------+---------------+---------+
a<0>           |c<1>           |    9.898|
a<0>           |c<2>           |   10.705|
a<0>           |c<3>           |   10.585|
a<0>           |c<4>           |   10.960|
a<0>           |c<5>           |   10.778|
a<0>           |c<6>           |   10.627|
a<0>           |c<7>           |   11.065|
a<1>           |c<1>           |   10.882|
a<1>           |c<2>           |   11.689|
a<1>           |c<3>           |   11.569|
a<1>           |c<4>           |   11.944|
a<1>           |c<5>           |   11.762|
a<1>           |c<6>           |   11.611|
a<1>           |c<7>           |   12.049|
a<2>           |c<1>           |   11.397|
a<2>           |c<2>           |   12.204|
a<2>           |c<3>           |   12.084|
a<2>           |c<4>           |   12.459|
a<2>           |c<5>           |   12.384|
a<2>           |c<6>           |   12.131|
a<2>           |c<7>           |   12.564|
a<3>           |c<1>           |   11.060|
a<3>           |c<2>           |   11.652|
a<3>           |c<3>           |   11.568|
a<3>           |c<4>           |   11.877|
a<3>           |c<5>           |   11.902|
a<3>           |c<6>           |   11.813|
a<3>           |c<7>           |   12.214|
---------------+---------------+---------+

Analysis completed Tue Mar 14 15:45:49 2006
--------------------------------------------------------------------------------



Peak Memory Usage: 62 MB

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