traffic.syr

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

Release 7.1.04i - xst H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: traffic.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "traffic.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "traffic"
Output Format                      : NGC
Target Device                      : xc2s50-6-TQ144

---- Source Options
Top Module Name                    : traffic
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : traffic.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
tristate2logic                     : Yes
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "traffic.v"
Module <traffic> compiled
No errors in compilation
Analysis of file <"traffic.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <traffic>.
	red = <u>00
	yellow = <u>01
	green = <u>10
Module <traffic> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <traffic>.
    Related source file is "traffic.v".
    Found finite state machine <FSM_0> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 9                                              |
    | Inputs             | 2                                              |
    | Outputs            | 15                                             |
    | Clock              | clk (rising_edge)                              |
    | Clock enable       | $n0000 (positive)                              |
    | Reset              | rst (negative)                                 |
    | Reset type         | asynchronous                                   |
    | Reset State        | 00                                             |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 16x8-bit ROM for signal <dataout>.
    Found 2-bit register for signal <en>.
    Found 4-bit subtractor for signal <$n0014> created at line 49.
    Found 4-bit subtractor for signal <$n0015> created at line 49.
    Found 26-bit adder for signal <$n0016> created at line 35.
    Found 26-bit register for signal <cnt>.
    Found 16-bit up counter for signal <cnt_scan>.
    Found 4-bit 4-to-1 multiplexer for signal <dataout_buf>.
    Found 4-bit register for signal <first>.
    Found 4-bit register for signal <second>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 ROM(s).
	inferred   1 Counter(s).
	inferred  30 D-type flip-flop(s).
	inferred   3 Adder/Subtractor(s).
	inferred   4 Multiplexer(s).
Unit <traffic> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <state[1:3]> with speed1 encoding.
-------------------
 State | Encoding
-------------------
 00    | 100
 01    | 001
 10    | 010
-------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# ROMs                             : 1
 16x8-bit ROM                      : 1
# Adders/Subtractors               : 3
 26-bit adder                      : 1
 4-bit subtractor                  : 2
# Counters                         : 1
 16-bit up counter                 : 1
# Registers                        : 7
 1-bit register                    : 3
 2-bit register                    : 1
 26-bit register                   : 1
 4-bit register                    : 2
# Multiplexers                     : 1
 4-bit 4-to-1 multiplexer          : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <traffic> ...
Loading device for application Rf_Device from file 'v50.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block traffic, actual ratio is 9.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : traffic.ngr
Top Level Output File Name         : traffic
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 24

Macro Statistics :
# ROMs                             : 1
#      16x8-bit ROM                : 1
# Registers                        : 11
#      1-bit register              : 8
#      16-bit register             : 1
#      26-bit register             : 1
#      4-bit register              : 1
# Multiplexers                     : 1
#      4-bit 4-to-1 multiplexer    : 1
# Adders/Subtractors               : 4
#      16-bit adder                : 1
#      26-bit adder                : 1
#      4-bit subtractor            : 2

Cell Usage :
# BELS                             : 218
#      GND                         : 1
#      INV                         : 8
#      LUT1                        : 16
#      LUT1_L                      : 24
#      LUT2                        : 4
#      LUT2_L                      : 28
#      LUT3                        : 2
#      LUT3_L                      : 1
#      LUT4                        : 26
#      LUT4_D                      : 8
#      LUT4_L                      : 15
#      MUXCY                       : 40
#      MUXF5                       : 3
#      MUXF6                       : 1
#      VCC                         : 1
#      XORCY                       : 40
# FlipFlops/Latches                : 55
#      FDC                         : 42
#      FDCE                        : 9
#      FDPE                        : 4
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 23
#      IBUF                        : 1
#      OBUF                        : 22
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-6 

 Number of Slices:                      69  out of    768     8%  
 Number of Slice Flip Flops:            55  out of   1536     3%  
 Number of 4 input LUTs:               124  out of   1536     8%  
 Number of bonded IOBs:                 24  out of     96    25%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 55    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 9.444ns (Maximum Frequency: 105.887MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 11.549ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 9.444ns (frequency: 105.887MHz)
  Total number of paths / destination ports: 1748 / 68
-------------------------------------------------------------------------
Delay:               9.444ns (Levels of Logic = 4)
  Source:            cnt_0 (FF)
  Destination:       cnt_10 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: cnt_0 to cnt_10
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              3   1.085   1.332  cnt_0 (cnt_0)
     LUT4:I3->O            1   0.549   1.035  Ker1383 (CHOICE58)
     LUT4_D:I2->O          3   0.549   1.332  Ker13109 (CHOICE66)
     LUT4_D:I3->O          7   0.549   1.755  _n00221_1 (_n00221)
     LUT2_L:I0->LO         1   0.549   0.000  _n0009<18>1 (_n0009<18>)
     FDC:D                     0.709          cnt_18
    ----------------------------------------
    Total                      9.444ns (3.990ns logic, 5.454ns route)
                                       (42.2% logic, 57.8% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 126 / 21
-------------------------------------------------------------------------
Offset:              11.549ns (Levels of Logic = 3)
  Source:            first_0 (FF)
  Destination:       dataout<7> (PAD)
  Source Clock:      clk rising

  Data Path: first_0 to dataout<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             9   1.085   1.908  first_0 (first_0)
     LUT4:I2->O            7   0.549   1.755  dataout_buf<0>1 (dataout_buf<0>)
     LUT4:I0->O            1   0.549   1.035  Mrom_dataout_inst_lut4_71 (dataout_7_OBUF)
     OBUF:I->O                 4.668          dataout_7_OBUF (dataout<7>)
    ----------------------------------------
    Total                     11.549ns (6.851ns logic, 4.698ns route)
                                       (59.3% logic, 40.7% route)

=========================================================================
CPU : 12.74 / 13.54 s | Elapsed : 13.00 / 13.00 s
 
--> 

Total memory usage is 75780 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    1 (   0 filtered)