traffic.rpt

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

 
cpldfit:  version H.42                              Xilinx Inc.
                                  Fitter Report
Design Name: traffic                             Date:  2-21-2006,  4:39PM
Device Used: XC95144XL-10-TQ144
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
79 /144 ( 55%) 382 /720  ( 53%) 231/432 ( 53%)   60 /144 ( 42%) 24 /117 ( 21%)

** Function Block Resources **

Function    Mcells      FB Inps     Pterms      IO          
Block       Used/Tot    Used/Tot    Used/Tot    Used/Tot    
FB1           8/18       38/54       76/90       0/15
FB2           4/18       38/54       47/90       0/15
FB3          12/18       42/54       42/90      12/15
FB4          14/18       28/54       75/90       3/15
FB5           7/18        9/54       21/90       0/14
FB6          18/18*      38/54       57/90       6/13
FB7           0/18        0/54        0/90       0/15
FB8          16/18       38/54       64/90       1/15
             -----       -----       -----      -----    
             79/144     231/432     382/720     22/117

* - Resource is exhausted

** Global Control Resources **

Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :    2           2    |  I/O              :    24     109
Output        :   22          22    |  GCK/IO           :     0       3
Bidirectional :    0           0    |  GTS/IO           :     0       4
GCK           :    0           0    |  GSR/IO           :     0       1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     24          24

** Power Data **

There are 79 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
**************************  Errors and Warnings  ***************************

WARNING:Cpld:896 - Unable to map all desired signals into function block, FB3,
   because too many function block product terms are required. Buffering output
   signal lightY<0> to allow all signals assigned to this function block to be
   placed.
WARNING:Cpld:896 - Unable to map all desired signals into function block, FB3,
   because too many function block product terms are required. Buffering output
   signal lightY<1> to allow all signals assigned to this function block to be
   placed.
WARNING:Cpld:896 - Unable to map all desired signals into function block, FB3,
   because too many function block product terms are required. Buffering output
   signal lightY<2> to allow all signals assigned to this function block to be
   placed.
WARNING:Cpld:896 - Unable to map all desired signals into function block, FB3,
   because too many function block product terms are required. Buffering output
   signal lightG<0> to allow all signals assigned to this function block to be
   placed.
WARNING:Cpld:896 - Unable to map all desired signals into function block, FB6,
   because too many function block product terms are required. Buffering output
   signal dataout<7> to allow all signals assigned to this function block to be
   placed.
WARNING:Cpld:896 - Unable to map all desired signals into function block, FB6,
   because too many function block product terms are required. Buffering output
   signal dataout<4> to allow all signals assigned to this function block to be
   placed.
WARNING:Cpld:896 - Unable to map all desired signals into function block, FB6,
   because too many function block product terms are required. Buffering output
   signal dataout<2> to allow all signals assigned to this function block to be
   placed.
*************************  Summary of Mapped Logic  ************************

** 22 Outputs **

Signal              Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                Pts   Inps          No.  Type    Use     Mode Rate State
lightG<3>           5     38    FB3_1   39   I/O     O       STD  FAST SET
lightY<3>           5     38    FB3_3   41   I/O     O       STD  FAST SET
lightY<2>           1     1     FB3_4   44   I/O     O       STD  FAST 
lightG<1>           12    38    FB3_5   33   I/O     O       STD  FAST SET
lightG<2>           12    38    FB3_6   34   I/O     O       STD  FAST SET
lightG<0>           1     1     FB3_9   40   I/O     O       STD  FAST 
lightR<0>           1     2     FB3_10  48   I/O     O       STD  FAST 
lightY<1>           1     1     FB3_11  43   I/O     O       STD  FAST 
lightY<0>           1     1     FB3_12  45   I/O     O       STD  FAST 
lightR<2>           1     2     FB3_14  49   I/O     O       STD  FAST 
lightR<1>           1     2     FB3_15  50   I/O     O       STD  FAST 
lightR<3>           1     2     FB3_17  51   I/O     O       STD  FAST 
dataout<1>          9     10    FB4_1   118  I/O     O       STD  FAST 
en<0>               3     18    FB4_9   131  I/O     O       STD  FAST RESET
en<1>               3     18    FB4_11  132  I/O     O       STD  FAST RESET
dataout<7>          1     1     FB6_2   106  I/O     O       STD  FAST 
dataout<5>          9     10    FB6_4   111  I/O     O       STD  FAST 
dataout<4>          1     1     FB6_8   113  I/O     O       STD  FAST 
dataout<2>          1     1     FB6_9   116  I/O     O       STD  FAST 
dataout<3>          9     10    FB6_10  115  I/O     O       STD  FAST 
dataout<0>          0     0     FB6_11  119  I/O     O       STD  FAST 
dataout<6>          12    10    FB8_16  107  I/O     O       STD  FAST 

** 57 Buried Nodes **

Signal              Total Total Loc     Pwr  Reg Init
Name                Pts   Inps          Mode State
first<2>            11    38    FB1_1   STD  RESET
lightY<2>_BUFR      12    38    FB1_4   STD  SET
second<3>           5     38    FB1_5   STD  RESET
first<0>            6     38    FB1_9   STD  RESET
lightY<1>_BUFR      12    38    FB1_10  STD  SET
lightY<0>_BUFR      12    38    FB1_13  STD  SET
second<2>           7     38    FB1_16  STD  RESET
second<1>           11    38    FB1_18  STD  RESET
first<1>            13    38    FB2_3   STD  RESET
first<3>            9     37    FB2_5   STD  RESET
second<0>           13    38    FB2_14  STD  RESET
lightG<0>_BUFR      12    38    FB2_17  STD  SET
cnt_scan<9>         3     11    FB4_2   STD  RESET
cnt_scan<8>         3     10    FB4_3   STD  RESET
cnt_scan<15>        3     17    FB4_4   STD  RESET
cnt_scan<14>        3     16    FB4_5   STD  RESET
cnt_scan<13>        3     15    FB4_6   STD  RESET
cnt_scan<12>        3     14    FB4_7   STD  RESET
cnt_scan<11>        3     13    FB4_8   STD  RESET
cnt_scan<10>        3     12    FB4_10  STD  RESET
dataout<7>_BUFR     12    10    FB4_12  STD  
dataout<4>_BUFR     12    10    FB4_16  STD  
dataout<2>_BUFR     12    10    FB4_18  STD  
cnt_scan<7>         3     9     FB5_12  STD  RESET
cnt_scan<6>         3     8     FB5_13  STD  RESET
cnt_scan<5>         3     7     FB5_14  STD  RESET
cnt_scan<4>         3     6     FB5_15  STD  RESET
cnt_scan<3>         3     5     FB5_16  STD  RESET
cnt_scan<2>         3     4     FB5_17  STD  RESET
cnt_scan<1>         3     3     FB5_18  STD  RESET
cnt<8>              3     10    FB6_1   STD  RESET
cnt<7>              3     9     FB6_3   STD  RESET
cnt<6>              3     8     FB6_5   STD  RESET
cnt<5>              3     7     FB6_6   STD  RESET
cnt<23>             3     25    FB6_7   STD  RESET
cnt<20>             3     22    FB6_12  STD  RESET
cnt<19>             3     21    FB6_13  STD  RESET
cnt<18>             3     20    FB6_14  STD  RESET
cnt<16>             3     18    FB6_15  STD  RESET
cnt<15>             3     17    FB6_16  STD  RESET

Signal              Total Total Loc     Pwr  Reg Init
Name                Pts   Inps          Mode State
cnt<13>             3     15    FB6_17  STD  RESET
cnt<10>             3     12    FB6_18  STD  RESET
cnt_scan<0>         2     2     FB8_2   STD  RESET
cnt<4>              3     6     FB8_3   STD  RESET
cnt<3>              3     5     FB8_4   STD  RESET
cnt<2>              3     4     FB8_5   STD  RESET
cnt<24>             3     26    FB8_6   STD  RESET
cnt<1>              3     3     FB8_7   STD  RESET
cnt<0>              3     28    FB8_8   STD  RESET
cnt<9>              4     28    FB8_9   STD  RESET
cnt<25>             4     28    FB8_10  STD  RESET
cnt<22>             4     28    FB8_11  STD  RESET
cnt<21>             4     28    FB8_12  STD  RESET
cnt<17>             4     28    FB8_13  STD  RESET
cnt<14>             4     28    FB8_14  STD  RESET
cnt<12>             4     28    FB8_17  STD  RESET
cnt<11>             4     28    FB8_18  STD  RESET

** 2 Inputs **

Signal              Loc     Pin  Pin     Pin     
Name                        No.  Type    Use     
clk                 FB4_5   128  I/O     I
rst                 FB7_2   71   I/O     I

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X            - Signal used as input to the macrocell logic.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               38/16
Number of signals used by logic mapping into function block:  38
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
first<2>             11       6<-   0   0     FB1_1   23    I/O     (b)
(unused)              0       0   /\5   0     FB1_2   16    I/O     (b)
(unused)              0       0   \/5   0     FB1_3   17    I/O     (b)
lightY<2>_BUFR       12       7<-   0   0     FB1_4   25    I/O     (b)
second<3>             5       2<- /\2   0     FB1_5   19    I/O     (b)
(unused)              0       0   /\2   3     FB1_6   20    I/O     (b)
(unused)              0       0     0   5     FB1_7         (b)     
(unused)              0       0   \/3   2     FB1_8   21    I/O     (b)
first<0>              6       3<- \/2   0     FB1_9   22    I/O     (b)
lightY<1>_BUFR       12       7<-   0   0     FB1_10  31    I/O     (b)
(unused)              0       0   /\5   0     FB1_11  24    I/O     (b)
(unused)              0       0   \/5   0     FB1_12  26    I/O     (b)
lightY<0>_BUFR       12       7<-   0   0     FB1_13        (b)     (b)
(unused)              0       0   /\2   3     FB1_14  27    I/O     (b)
(unused)              0       0   \/4   1     FB1_15  28    I/O     (b)
second<2>             7       4<- \/2   0     FB1_16  35    I/O     (b)
(unused)              0       0   \/5   0     FB1_17  30    GCK/I/O (b)
second<1>            11       7<- \/1   0     FB1_18        (b)     (b)

Signals Used by Logic in Function Block
  1: clk               14: cnt<20>           27: cnt<9> 
  2: cnt<0>            15: cnt<21>           28: first<0> 
  3: cnt<10>           16: cnt<22>           29: first<1> 
  4: cnt<11>           17: cnt<23>           30: first<2> 
  5: cnt<12>           18: cnt<24>           31: first<3> 
  6: cnt<13>           19: cnt<25>           32: lightG<3> 
  7: cnt<14>           20: cnt<2>            33: lightY<3> 
  8: cnt<15>           21: cnt<3>            34: rst 
  9: cnt<16>           22: cnt<4>            35: second<0> 
 10: cnt<17>           23: cnt<5>            36: second<1> 
 11: cnt<18>           24: cnt<6>            37: second<2> 
 12: cnt<19>           25: cnt<7>            38: second<3> 
 13: cnt<1>            26: cnt<8>           

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
first<2>             XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX.. 38
lightY<2>_BUFR       XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX.. 38
second<3>            XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX.. 38
first<0>             XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX.. 38
lightY<1>_BUFR       XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX.. 38
lightY<0>_BUFR       XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX.. 38
second<2>            XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX.. 38
second<1>            XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX.. 38
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB2  ***********************************